Abstract

Most of today’s digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools.

In special cases such as synthesis for coarse-grain cell libraries or when testing new synthesis algorithms it might be necessary to write a custom HDL synthesis tool or add new features to an existing one. In these cases the availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful.

In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was developed. This document covers the design and implementation of this tool. At the moment the main focus of Yosys lies on the high-level aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used by Yosys to perform advanced gate-level optimizations.

An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced by Yosys in this tests where successfully verified using formal verification and are comparable in quality to the results produced by a commercial synthesis tool.

This document was originally published as bachelor thesis at the Vienna University of Technology [Wol13].

Yosys manual

Manual

• 1. Introduction
  • 1.1. History of Yosys
  • 1.2. Structure of this document
• 2. Basic principles
  • 2.1. Levels of abstraction
  • 2.2. Features of synthesizable Verilog
  • 2.3. Challenges in digital circuit synthesis
  • 2.4. Script-based synthesis flows
  • 2.5. Methods from compiler design
• 3. Approach
  • 3.1. Data- and control-flow
  • 3.2. Internal formats in Yosys
  • 3.3. Typical use case
• 4. Implementation overview
  • 4.1. Simplified data flow
  • 4.2. The RTL Intermediate Language (RTLIL)
  • 4.3. Command interface and synthesis scripts
  • 4.4. Source tree and build system
• 5. Internal cell library
  • 5.1. RTL cells
  • 5.2. Gates
• 6. Programming Yosys extensions
  • 6.1. Guidelines
  • 6.2. The “stubsnets” example module
• 7. The Verilog and AST frontends
  • 7.1. Transforming Verilog to AST
  • 7.2. Transforming AST to RTLIL
  • 7.3. Synthesizing Verilog always blocks
  • 7.4. Synthesizing Verilog arrays
  • 7.5. Synthesizing parametric designs
• 8. Optimizations
  • 8.1. Simple optimizations
  • 8.2. FSM extraction and encoding
  • 8.3. Logic optimization
• 9. Technology mapping
  • 9.1. Cell substitution
  • 9.2. Subcircuit substitution
  • 9.3. Gate-level technology mapping
• 10. Memory mapping
  • 10.1. Additional notes
  • 10.2. Simple dual port (SDP) memory patterns
  • 10.3. Single-port RAM memory patterns
  • 10.4. Read register reset patterns
  • 10.5. Asymmetric memory patterns
  • 10.6. True dual port (TDP) patterns
  • 10.7. Not yet supported patterns
  • 10.8. Undesired patterns

Appendix

• Auxiliary libraries
  • SHA1
  • BigInt
  • SubCircuit
  • ezSAT
• Auxiliary programs
  • yosys-config
  • yosys-filterlib
  • yosys-abc
• RTLIL text representation
  • Lexical elements
  • File
• 010: Converting Verilog to BLIF page
  • Installation
  • Getting started
  • Using a synthesis script
  • Advanced example: The Amber23 ARMv2a CPU
  • Verification of the Amber23 CPU
  • Limitations
  • Conclusion
• 011: Interactive design investigation page
  • Installation and prerequisites
  • Overview
  • Introduction to the show command
  • Navigating the design
  • Advanced investigation techniques
  • Conclusion
• 012: Converting Verilog to BTOR page
  • Installation
  • Quick start
  • Detailed flow
  • Example
  • Limitations
  • Conclusion
• Literature references

• Command line reference