Appendix# A primer on digital circuit synthesis Levels of abstraction Features of synthesizable Verilog Challenges in digital circuit synthesis Script-based synthesis flows Methods from compiler design Auxiliary libraries BigInt dlfcn-win32 ezSAT fst json11 MiniSAT SHA1 SubCircuit Auxiliary programs yosys-config yosys-filterlib yosys-abc yosys-smtbmc yosys-witness Literature references Command line reference