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clockgate - extract clock gating out of flip flops
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.. cmd:def:: clockgate
   :title: extract clock gating out of flip flops

   .. only:: html



      .. code:: yoscrypt

         clockgate [options] [selection]

      ::

         This pass transforms each set of FFs sharing the same clock and
         enable signal into a clock-gating cell and a set of enable-less FFs.
         Primarily a power-saving transformation on ASIC designs.


      .. code:: yoscrypt

         -pos <celltype> <ce>:<clk>:<gclk>

      ::

             If specified, rising-edge FFs will have CE inputs
             removed and a gated clock will be created by the
             user-specified <celltype> ICG (integrated clock gating)
             cell with ports named <ce>, <clk>, <gclk>.
             The ICG's clock enable pin must be active high.

      ::

         -neg <celltype> <ce>:<clk>:<gclk>
             If specified, falling-edge FFs will have CE inputs
             removed and a gated clock will be created by the
             user-specified <celltype> ICG (integrated clock gating)
             cell with ports named <ce>, <clk>, <gclk>.
             The ICG's clock enable pin must be active high.

      ::

         -tie_lo <port_name>
             Port <port_name> of the ICG will be tied to zero.
             Intended for DFT scan-enable pins.

      ::

         -min_net_size <n>
             Only transform sets of at least <n> eligible FFs.
.. only:: latex

   ::

      
          clockgate [options] [selection]
      
      This pass transforms each set of FFs sharing the same clock and
      enable signal into a clock-gating cell and a set of enable-less FFs.
      Primarily a power-saving transformation on ASIC designs.
      
          -pos <celltype> <ce>:<clk>:<gclk>
              If specified, rising-edge FFs will have CE inputs
              removed and a gated clock will be created by the
              user-specified <celltype> ICG (integrated clock gating)
              cell with ports named <ce>, <clk>, <gclk>.
              The ICG's clock enable pin must be active high.
          -neg <celltype> <ce>:<clk>:<gclk>
              If specified, falling-edge FFs will have CE inputs
              removed and a gated clock will be created by the
              user-specified <celltype> ICG (integrated clock gating)
              cell with ports named <ce>, <clk>, <gclk>.
              The ICG's clock enable pin must be active high.
          -tie_lo <port_name>
              Port <port_name> of the ICG will be tied to zero.
              Intended for DFT scan-enable pins.
          -min_net_size <n>
              Only transform sets of at least <n> eligible FFs.