abc9_ops - helper functions for ABC9

yosys> help abc9_ops
abc9_ops [options] [selection]
This pass contains a set of supporting operations for use during ABC technology
mapping, and is expected to be called in conjunction with other operations from
the `abc9' script pass. Only fully-selected modules are supported.
check that the design is valid, e.g. (* abc9_box_id *) values are
unique, (* abc9_carry *) is only given for one input/output port, etc.
derive all used (* abc9_box *) or (* abc9_flop *) (if -dff option)
whitebox modules. with (* abc9_flop *) modules, only those containing
$dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC
limitation -- will be derived.
create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for
bypassing sequential (* abc9_box *) modules using a combinatorial box
(named *_$abc9_byp). bypassing is necessary if sequential elements (e.g.
$dff, $mem, etc.) are discovered inside so that any combinatorial paths
will be correctly captured. this bypass box will only contain ports that
are referenced by a simple path declaration ($specify2 cell) inside a
specify block.
select all (* abc9_flop *) modules instantiated in the design and store
in the named selection '$abc9_flops'.
within (* abc9_flop *) modules, rewrite all edge-sensitive path
declarations and $setup() timing checks ($specify3 and $specrule cells)
that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port
to the DFF's 'D' port. this is to prepare such specify cells to be moved
into the flop box.
populate the '$abc9_unmap' design with techmap rules for mapping
*_$abc9_flop cells back into their derived cell types (where the rules
created by -prep_hier will then map back to the original cell with
insert `$__ABC9_DELAY' blackbox cells into the design to account for
certain required times.
for an arbitrarily chosen cell in each unique SCC of each selected
module (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt
all wires driven by this cell's outputs with a temporary
$__ABC9_SCC_BREAKER cell to break the SCC.
prepare the design for XAIGER output. this includes computing the
topological ordering of ABC9 boxes, as well as preparing the
'$abc9_holes' design that contains the logic behaviour of ABC9
consider flop cells (those instantiating modules marked with
(* abc9_flop *)) during -prep_{delays,xaiger,box}.
-prep_lut <maxlut>
pre-compute the lut library by analysing all modules marked with
(* abc9_lut=<area> *).
-write_lut <dst>
write the pre-computed lut library to <dst>.
pre-compute the box library by analysing all modules marked with
(* abc9_box *).
-write_box <dst>
write the pre-computed box library to <dst>.
for each selected module, re-intergrate the module '<module-name>$abc9'
by first recovering ABC9 boxes, and then stitching in the remaining
primary inputs and outputs.