clockgate - extract clock gating out of flip flops

yosys> help clockgate

clockgate [options] [selection]

This pass transforms each set of FFs sharing the same clock and
enable signal into a clock-gating cell and a set of enable-less FFs.
Primarily a power-saving transformation on ASIC designs.

-pos <celltype> <ce>:<clk>:<gclk>

If specified, rising-edge FFs will have CE inputs
removed and a gated clock will be created by the
user-specified <celltype> ICG (integrated clock gating)
cell with ports named <ce>, <clk>, <gclk>.
The ICG's clock enable pin must be active high.

-neg <celltype> <ce>:<clk>:<gclk>
    If specified, falling-edge FFs will have CE inputs
    removed and a gated clock will be created by the
    user-specified <celltype> ICG (integrated clock gating)
    cell with ports named <ce>, <clk>, <gclk>.
    The ICG's clock enable pin must be active high.

-liberty <filename>
    If specified, ICGs will be selected from the liberty file
    if available. Priority is given to cells with fewer tie_lo
    inputs and smaller size. This removes the need to manually
    specify -pos or -neg and -tie_lo.

-dont_use <celltype>
    Cells <celltype> won't be considered when searching for ICGs
    in the liberty file specified by -liberty.

-tie_lo <port_name>
    Port <port_name> of the ICG will be tied to zero.
    Intended for DFT scan-enable pins.

-min_net_size <n>
    Only transform sets of at least <n> eligible FFs.