expose - convert internal signals to module ports¶
yosys> help expose¶
expose [options] [selection]
This command exposes all selected internal signals of a module as additional outputs.
only consider wires that are directly driven by register cell.
when exposing a wire, create an input/output pair and cut the internal signal path at that wire.
when exposing a wire, create an input port and disconnect the internal driver.
only expose those signals that are shared among the selected modules. this is useful for preparing modules for equivalence checking.
also turn connections to instances of other modules to additional inputs and outputs and remove the module instances.
turn flip-flops to sets of inputs and outputs.
when creating new wire/port names, the original object name is suffixed with this separator (default: '.') and the port name or a type designator for the exposed signal.