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YosysHQ Yosys 0.51-dev documentation

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Yosys (index)
What is Yosys
Getting started with Yosys
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Using Yosys (advanced)
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- Synthesis in detail
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- More scripting
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Yosys internals
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- Internal flow
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- Internal formats
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  - The RTL Intermediate Language (RTLIL)
- Working with the Yosys codebase
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- Techmap by example
- Notes on Verilog support in Yosys
- Hashing and associative data structures in Yosys

Appendix

A primer on digital circuit synthesis
RTLIL text representation
Auxiliary libraries
Auxiliary programs
Literature references
Internal cell library
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- Word-level cells
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- Gate-level cells
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- Cell properties
Command line reference
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internal_stats - print internal statistics¶

yosys> help internal_stats¶

Print internal statistics for developers (experimental)

iopadmap - technology mapping of i/o pads (or buffers)

insbuf - insert buffer cells for connected wires

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