memory_map - translate multiport memories to basic cells

yosys> help memory_map
memory_map [options] [selection]
This pass converts multiport memory cells as generated by the memory_collect
pass to word-wide DFFs and address decoders.
-attr !<name>
do not map memories that have attribute <name> set.
-attr <name>[=<value>]
for memories that have attribute <name> set, only map them if its value
is a string <value> (if specified), or an integer 1 (otherwise). if this
option is specified multiple times, map the memory if the attribute is
to any of the values.
for -attr, suppress case sensitivity in matching of <value>.
only perform conversion for ROMs (memories with no write ports).
when mapping ROMs, keep x-bits shared across read ports.
map memories for a global clock based formal verification flow.
This implies -keepdc, uses $ff cells for ROMs and sets hdlname
attributes. It also has limited support for async write ports
as generated by clk2fflogic.