prep - generic synthesis script¶
yosys> help prep¶
This command runs a conservative RTL synthesis. A typical application for this is the preparation stage of a verification flow. This command does not operate on partly selected designs.
use the specified module as top module (default='top')
automatically determine the top of the design hierarchy
flatten the design before synthesis. this will pass '-auto-top' to 'hierarchy' if no top module is specified.
passed to 'proc'. uses verilog simulation behavior for verilog if/case undef handling. this also prevents 'wreduce' from being run.
simulate verilog simulation behavior for out-of-bounds memory accesses using the 'memory_memx' pass.
do not run any of the memory_* passes
call 'memory_dff'. This enables merging of FFs into memory read ports.
do not call opt_* with -keepdc
only run the commands between the labels (see below). an empty from label is synonymous to 'begin', and empty to label is synonymous to the end of the command list.
The following commands are executed by this synthesis command: begin: hierarchy -check [-top <top> | -auto-top] coarse: proc [-ifx] flatten (if -flatten) future opt_expr -keepdc opt_clean check opt -noff -keepdc wreduce -keepdc [-memx] memory_dff (if -rdff) memory_memx (if -memx) opt_clean memory_collect opt -noff -keepdc -fast check: stat check