synth - generic synthesis script¶
yosys> help synth¶
This command runs the default synthesis script. This command does not operate on partly selected designs.
use the specified module as top module (default='top')
automatically determine the top of the design hierarchy
flatten the design before synthesis. this will pass '-auto-top' to 'hierarchy' if no top module is specified.
passed to 'fsm_recode' via 'fsm'
perform synthesis for a k-LUT architecture.
do not run FSM optimization
do not run abc (as if yosys was compiled without ABC support)
run the booth pass to convert $mul to Booth encoded multipliers
-noalumacc do not run 'alumacc' pass. i.e. keep arithmetic operators in their direct form ($add, $sub, etc.).
passed to 'memory'. prohibits merging of FFs into memory read ports
do not run SAT-based resource sharing
only run the commands between the labels (see below). an empty from label is synonymous to 'begin', and empty to label is synonymous to the end of the command list.
use new ABC9 flow (EXPERIMENTAL)
use FlowMap LUT techmapping instead of ABC
marks all recognized read ports as "return don't-care value on read/write collision" (same result as setting the no_rw_check attribute on all memories).
The following commands are executed by this synthesis command: begin: hierarchy -check [-top <top> | -auto-top] coarse: proc flatten (if -flatten) opt_expr opt_clean check opt -nodffe -nosdff fsm (unless -nofsm) opt wreduce peepopt opt_clean techmap -map +/cmp2lut.v -map +/cmp2lcu.v (if -lut) alumacc (unless -noalumacc) share (unless -noshare) opt memory -nomap opt_clean fine: opt -fast -full memory_map opt -full techmap techmap -map +/gate2lut.v (if -noabc and -lut) clean; opt_lut (if -noabc and -lut) flowmap -maxlut K (if -flowmap and -lut) opt -fast abc -fast (unless -noabc, unless -lut) abc -fast -lut k (unless -noabc, if -lut) opt -fast (unless -noabc) check: hierarchy -check stat check