Appendix¶
- yosys> help $alu¶
A building block supporting both binary addition/subtraction operations, and indirectly, comparison operations. Typically created by the
alumacc
pass, which transforms:$add
,$sub
,$lt
,$le
,$ge
,$gt
,$eq
,$eqx
,$ne
,$nex
cells into this$alu
cell.- Simulation model (verilog)¶
592module \$alu (A, B, CI, BI, X, Y, CO); 593 594 parameter A_SIGNED = 0; 595 parameter B_SIGNED = 0; 596 parameter A_WIDTH = 1; 597 parameter B_WIDTH = 1; 598 parameter Y_WIDTH = 1; 599 600 input [A_WIDTH-1:0] A; // Input operand 601 input [B_WIDTH-1:0] B; // Input operand 602 output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion, 603 // used in combination with 604 // reduction-AND for $eq/$ne ops) 605 output [Y_WIDTH-1:0] Y; // Sum 606 607 input CI; // Carry-in (set for $sub) 608 input BI; // Invert-B (set for $sub) 609 output [Y_WIDTH-1:0] CO; // Carry-out 610 611 wire [Y_WIDTH-1:0] AA, BB; 612 613 generate 614 if (A_SIGNED && B_SIGNED) begin:BLOCK1 615 assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B); 616 end else begin:BLOCK2 617 assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B); 618 end 619 endgenerate 620 621 // this is 'x' if Y and CO should be all 'x', and '0' otherwise 622 wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI}; 623 624 assign X = AA ^ BB; 625 // Full adder 626 assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}}; 627 628 function get_carry; 629 input a, b, c; 630 get_carry = (a&b) | (a&c) | (b&c); 631 endfunction 632 633 genvar i; 634 generate 635 assign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef; 636 for (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3 637 assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef; 638 end 639 endgenerate 640 641endmodule
- yosys> help $lcu¶
Lookahead carry unit A building block dedicated to fast computation of carry-bits used in binary arithmetic operations. By replacing the ripple carry structure used in full-adder blocks, the more significant bits of the sum can be expected to be computed more quickly. Typically created during
techmap
of $alu cells (see the “_90_alu” rule in +/techmap.v).