synth_nanoxplore - synthesis for NanoXplore FPGAs

yosys> help synth_nanoxplore

synth_nanoxplore [options]

This command runs synthesis for NanoXplore FPGAs.

-top <module>

use the specified module as top module

-family <family>

run synthesis for the specified NanoXplore architecture
generate the synthesis netlist for the specified family.
supported values:
- medium: NG-Medium
- large: NG-Large
- ultra: NG-Ultra

-json <file>

write the design to the specified JSON file. writing of an output file
is omitted if this parameter is not specified.

-run <from_label>:<to_label>

only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.

-noflatten

do not flatten design before synthesis

-abc9

use new ABC9 flow (EXPERIMENTAL)

-nocy

do not map adders to CY cells

-nodffe

do not use flipflops with L in output netlist

-min_ce_use <min_ce_use>

do not use flip-flops with load signal if the resulting count is less
than min_ce_use in output netlist

-min_srst_use <min_srst_use>

do not use flip-flops with async reset signal if the resulting count is less
than min_srst_use in output netlist

-norfram

do not use Register File RAM cells in output netlist

-nobram

do not use block NX_RAM cells in output netlist

-noiopad

do not insert IO buffers

-no-rw-check

marks all recognized read ports as "return don't-care value on
read/write collision" (same result as setting the no_rw_check
attribute on all memories).

The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb.v
        techmap -map +/nanoxplore/cells_wrap.v
        techmap -map +/nanoxplore/cells_wrap.v
        hierarchy -check -top <top>

    coarse:
        proc
        flatten    (skip if -noflatten)
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean
        alumacc
        opt
        memory -nomap [-no-rw-check]
        opt_clean

    map_ram:
        memory_libmap -lib +/nanoxplore/rf_rams.txt -lib +/nanoxplore/brams.txt [-no-auto-block] [-no-auto-distributed]    (-no-auto-block if -nobram, -no-auto-distributed if -norfram)
        techmap -map +/nanoxplore/rf_rams_map.v -map +/nanoxplore/brams_map.v
        techmap -map +/nanoxplore/cells_wrap.v t:NX_RAM*
        techmap -map +/nanoxplore/cells_wrap.v t:NX_XRFB* t:NX_RFB*

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine -mux_undef

    map_gates:
        techmap -map +/techmap.v -map +/nanoxplore/arith_map.v
        nx_carry
        iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top    (skip if '-noiopad')
        techmap -map +/nanoxplore/io_map.v
        opt -fast

    map_ffs:
        dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r [-cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r] -cell $_DLATCH_?_ x -mince 8 -minsrst 8    ($_*DFFE_* only if not -nodffe)
        opt_merge
        techmap -map +/nanoxplore/latches_map.v
        techmap -map +/nanoxplore/cells_map.v
        opt_expr -undriven -mux_undef
        clean -purge

    map_luts:
        abc -dress -lut 4
        techmap -map +/nanoxplore/cells_map.v t:$lut
        opt -fast
        clean

    check:
        autoname
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox
        setundef -zero -undriven

    json:
        write_json <file-name>