synthprop - synthesize SVA properties

yosys> help synthprop

synthprop [options]

This creates synthesizable properties for the selected module.

-name <portname>

name of the output port for assertions (default: assertions).

-map <filename>

write the port mapping for synthesizable properties into the given file.

-or_outputs

Or all outputs together to create a single output that goes high when
any property is violated, instead of generating individual output bits.

-reset <portname>

name of the top-level reset input. Latch a high state on the generated
outputs until an asynchronous top-level reset input is activated.

-resetn <portname>

like above but with inverse polarity