Flip-flop cells

The cell types $_DFF_N_ and $_DFF_P_ represent d-type flip-flops.

Table 9 Cell types for basic flip-flops

Verilog

Cell Type

always @(negedge C) Q <= D

$_DFF_N_

always @(posedge C) Q <= D

$_DFF_P_

The cell types $_DFFE_[NP][NP]_ implement d-type flip-flops with enable. The values in the table for these cell types relate to the following Verilog code template.

always @(CLK_EDGE C)
   if (EN == EN_LVL)
      Q <= D;
Table 10 Cell types for gate level logic networks (FFs with enable)

\(ClkEdge\)

\(EnLvl\)

Cell Type

negedge

0

$_DFFE_NN_

negedge

1

$_DFFE_NP_

posedge

0

$_DFFE_PN_

posedge

1

$_DFFE_PP_

The cell types $_DFF_[NP][NP][01]_ implement d-type flip-flops with asynchronous reset. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, and negedge otherwise.

always @(CLK_EDGE C, RST_EDGE R)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else
      Q <= D;

The cell types $_SDFF_[NP][NP][01]_ implement d-type flip-flops with synchronous reset. The values in the table for these cell types relate to the following Verilog code template:

always @(CLK_EDGE C)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else
      Q <= D;
Table 11 Cell types for gate level logic networks (FFs with reset)

\(ClkEdge\)

\(RstLvl\)

\(RstVal\)

Cell Type

negedge

0

0

$_DFF_NN0_, $_SDFF_NN0_

negedge

0

1

$_DFF_NN1_, $_SDFF_NN1_

negedge

1

0

$_DFF_NP0_, $_SDFF_NP0_

negedge

1

1

$_DFF_NP1_, $_SDFF_NP1_

posedge

0

0

$_DFF_PN0_, $_SDFF_PN0_

posedge

0

1

$_DFF_PN1_, $_SDFF_PN1_

posedge

1

0

$_DFF_PP0_, $_SDFF_PP0_

posedge

1

1

$_DFF_PP1_, $_SDFF_PP1_

The cell types $_DFFE_[NP][NP][01][NP]_ implement d-type flip-flops with asynchronous reset and enable. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, and negedge otherwise.

always @(CLK_EDGE C, RST_EDGE R)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else if (EN == EN_LVL)
      Q <= D;

The cell types $_SDFFE_[NP][NP][01][NP]_ implement d-type flip-flops with synchronous reset and enable, with reset having priority over enable. The values in the table for these cell types relate to the following Verilog code template:

always @(CLK_EDGE C)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else if (EN == EN_LVL)
      Q <= D;

The cell types $_SDFFCE_[NP][NP][01][NP]_ implement d-type flip-flops with synchronous reset and enable, with enable having priority over reset. The values in the table for these cell types relate to the following Verilog code template:

always @(CLK_EDGE C)
   if (EN == EN_LVL)
      if (R == RST_LVL)
         Q <= RST_VAL;
      else
         Q <= D;
Table 12 Cell types for gate level logic networks (FFs with reset and enable)

\(ClkEdge\)

\(RstLvl\)

\(RstVal\)

\(EnLvl\)

Cell Type

negedge

0

0

0

$_DFFE_NN0N_, $_SDFFE_NN0N_, $_SDFFCE_NN0N_

negedge

0

0

1

$_DFFE_NN0P_, $_SDFFE_NN0P_, $_SDFFCE_NN0P_

negedge

0

1

0

$_DFFE_NN1N_, $_SDFFE_NN1N_, $_SDFFCE_NN1N_

negedge

0

1

1

$_DFFE_NN1P_, $_SDFFE_NN1P_, $_SDFFCE_NN1P_

negedge

1

0

0

$_DFFE_NP0N_, $_SDFFE_NP0N_, $_SDFFCE_NP0N_

negedge

1

0

1

$_DFFE_NP0P_, $_SDFFE_NP0P_, $_SDFFCE_NP0P_

negedge

1

1

0

$_DFFE_NP1N_, $_SDFFE_NP1N_, $_SDFFCE_NP1N_

negedge

1

1

1

$_DFFE_NP1P_, $_SDFFE_NP1P_, $_SDFFCE_NP1P_

posedge

0

0

0

$_DFFE_PN0N_, $_SDFFE_PN0N_, $_SDFFCE_PN0N_

posedge

0

0

1

$_DFFE_PN0P_, $_SDFFE_PN0P_, $_SDFFCE_PN0P_

posedge

0

1

0

$_DFFE_PN1N_, $_SDFFE_PN1N_, $_SDFFCE_PN1N_

posedge

0

1

1

$_DFFE_PN1P_, $_SDFFE_PN1P_, $_SDFFCE_PN1P_

posedge

1

0

0

$_DFFE_PP0N_, $_SDFFE_PP0N_, $_SDFFCE_PP0N_

posedge

1

0

1

$_DFFE_PP0P_, $_SDFFE_PP0P_, $_SDFFCE_PP0P_

posedge

1

1

0

$_DFFE_PP1N_, $_SDFFE_PP1N_, $_SDFFCE_PP1N_

posedge

1

1

1

$_DFFE_PP1P_, $_SDFFE_PP1P_, $_SDFFCE_PP1P_

The cell types $_DFFSR_[NP][NP][NP]_ implement d-type flip-flops with asynchronous set and reset. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, negedge otherwise, and SET_EDGE is posedge if SET_LVL if 1, negedge otherwise.

When both set and reset are active, the state and output is undefined. The Verilog code model does not correspond to this due to limitations of synthesizable Verilog.

always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S)
   if (R == RST_LVL)
      Q <= 0;
   else if (S == SET_LVL)
      Q <= 1;
   else
      Q <= D;
Table 13 Cell types for gate level logic networks (FFs with set and reset)

\(ClkEdge\)

\(SetLvl\)

\(RstLvl\)

Cell Type

negedge

0

0

$_DFFSR_NNN_

negedge

0

1

$_DFFSR_NNP_

negedge

1

0

$_DFFSR_NPN_

negedge

1

1

$_DFFSR_NPP_

posedge

0

0

$_DFFSR_PNN_

posedge

0

1

$_DFFSR_PNP_

posedge

1

0

$_DFFSR_PPN_

posedge

1

1

$_DFFSR_PPP_

The cell types $_DFFSRE_[NP][NP][NP][NP]_ implement d-type flip-flops with asynchronous set and reset and enable. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, negedge otherwise, and SET_EDGE is posedge if SET_LVL if 1, negedge otherwise.

When both set and reset are active, the state and output is undefined. The Verilog code model does not correspond to this due to limitations of synthesizable Verilog.

always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S)
   if (R == RST_LVL)
      Q <= 0;
   else if (S == SET_LVL)
      Q <= 1;
   else if (E == EN_LVL)
      Q <= D;
Table 14 Cell types for gate level logic networks (FFs with set and reset and enable)

\(ClkEdge\)

\(SetLvl\)

\(RstLvl\)

\(EnLvl\)

Cell Type

negedge

0

0

0

$_DFFSRE_NNNN_

negedge

0

0

1

$_DFFSRE_NNNP_

negedge

0

1

0

$_DFFSRE_NNPN_

negedge

0

1

1

$_DFFSRE_NNPP_

negedge

1

0

0

$_DFFSRE_NPNN_

negedge

1

0

1

$_DFFSRE_NPNP_

negedge

1

1

0

$_DFFSRE_NPPN_

negedge

1

1

1

$_DFFSRE_NPPP_

posedge

0

0

0

$_DFFSRE_PNNN_

posedge

0

0

1

$_DFFSRE_PNNP_

posedge

0

1

0

$_DFFSRE_PNPN_

posedge

0

1

1

$_DFFSRE_PNPP_

posedge

1

0

0

$_DFFSRE_PPNN_

posedge

1

0

1

$_DFFSRE_PPNP_

posedge

1

1

0

$_DFFSRE_PPPN_

posedge

1

1

1

$_DFFSRE_PPPP_
yosys> help $_ALDFFE_NNN_

A negative edge D-type flip-flop with negative polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d \ - -  0 | d
                - - - -  - | q
Simulation model (verilog)
Listing 269 simcells.v
1420module \$_ALDFFE_NNN_ (D, C, L, AD, E, Q);
1421    input D, C, L, AD, E;
1422    output reg Q;
1423    always @(negedge C or negedge L) begin
1424        if (L == 0)
1425            Q <= AD;
1426        else if (E == 0)
1427            Q <= D;
1428    end
1429endmodule
yosys> help $_ALDFFE_NNP_

A negative edge D-type flip-flop with negative polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d \ - -  1 | d
                - - - -  - | q
Simulation model (verilog)
Listing 270 simcells.v
1445module \$_ALDFFE_NNP_ (D, C, L, AD, E, Q);
1446    input D, C, L, AD, E;
1447    output reg Q;
1448    always @(negedge C or negedge L) begin
1449        if (L == 0)
1450            Q <= AD;
1451        else if (E == 1)
1452            Q <= D;
1453    end
1454endmodule
yosys> help $_ALDFFE_NPN_

A negative edge D-type flip-flop with positive polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d \ - -  0 | d
                - - - -  - | q
Simulation model (verilog)
Listing 271 simcells.v
1470module \$_ALDFFE_NPN_ (D, C, L, AD, E, Q);
1471    input D, C, L, AD, E;
1472    output reg Q;
1473    always @(negedge C or posedge L) begin
1474        if (L == 1)
1475            Q <= AD;
1476        else if (E == 0)
1477            Q <= D;
1478    end
1479endmodule
yosys> help $_ALDFFE_NPP_

A negative edge D-type flip-flop with positive polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d \ - -  1 | d
                - - - -  - | q
Simulation model (verilog)
Listing 272 simcells.v
1495module \$_ALDFFE_NPP_ (D, C, L, AD, E, Q);
1496    input D, C, L, AD, E;
1497    output reg Q;
1498    always @(negedge C or posedge L) begin
1499        if (L == 1)
1500            Q <= AD;
1501        else if (E == 1)
1502            Q <= D;
1503    end
1504endmodule
yosys> help $_ALDFFE_PNN_

A positive edge D-type flip-flop with negative polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d / - -  0 | d
                - - - -  - | q
Simulation model (verilog)
Listing 273 simcells.v
1520module \$_ALDFFE_PNN_ (D, C, L, AD, E, Q);
1521    input D, C, L, AD, E;
1522    output reg Q;
1523    always @(posedge C or negedge L) begin
1524        if (L == 0)
1525            Q <= AD;
1526        else if (E == 0)
1527            Q <= D;
1528    end
1529endmodule
yosys> help $_ALDFFE_PNP_

A positive edge D-type flip-flop with negative polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d / - -  1 | d
                - - - -  - | q
Simulation model (verilog)
Listing 274 simcells.v
1545module \$_ALDFFE_PNP_ (D, C, L, AD, E, Q);
1546    input D, C, L, AD, E;
1547    output reg Q;
1548    always @(posedge C or negedge L) begin
1549        if (L == 0)
1550            Q <= AD;
1551        else if (E == 1)
1552            Q <= D;
1553    end
1554endmodule
yosys> help $_ALDFFE_PPN_

A positive edge D-type flip-flop with positive polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d / - -  0 | d
                - - - -  - | q
Simulation model (verilog)
Listing 275 simcells.v
1570module \$_ALDFFE_PPN_ (D, C, L, AD, E, Q);
1571    input D, C, L, AD, E;
1572    output reg Q;
1573    always @(posedge C or posedge L) begin
1574        if (L == 1)
1575            Q <= AD;
1576        else if (E == 0)
1577            Q <= D;
1578    end
1579endmodule
yosys> help $_ALDFFE_PPP_

A positive edge D-type flip-flop with positive polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d / - -  1 | d
                - - - -  - | q
Simulation model (verilog)
Listing 276 simcells.v
1595module \$_ALDFFE_PPP_ (D, C, L, AD, E, Q);
1596    input D, C, L, AD, E;
1597    output reg Q;
1598    always @(posedge C or posedge L) begin
1599        if (L == 1)
1600            Q <= AD;
1601        else if (E == 1)
1602            Q <= D;
1603    end
1604endmodule
yosys> help $_ALDFF_NN_

A negative edge D-type flip-flop with negative polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 0 a  | a
                d \ - -  | d
                - - - -  | q
Simulation model (verilog)
Listing 277 simcells.v
1323module \$_ALDFF_NN_ (D, C, L, AD, Q);
1324    input D, C, L, AD;
1325    output reg Q;
1326    always @(negedge C or negedge L) begin
1327        if (L == 0)
1328            Q <= AD;
1329        else
1330            Q <= D;
1331    end
1332endmodule
yosys> help $_ALDFF_NP_

A negative edge D-type flip-flop with positive polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 1 a  | a
                d \ - -  | d
                - - - -  | q
Simulation model (verilog)
Listing 278 simcells.v
1347module \$_ALDFF_NP_ (D, C, L, AD, Q);
1348    input D, C, L, AD;
1349    output reg Q;
1350    always @(negedge C or posedge L) begin
1351        if (L == 1)
1352            Q <= AD;
1353        else
1354            Q <= D;
1355    end
1356endmodule
yosys> help $_ALDFF_PN_

A positive edge D-type flip-flop with negative polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 0 a  | a
                d / - -  | d
                - - - -  | q
Simulation model (verilog)
Listing 279 simcells.v
1371module \$_ALDFF_PN_ (D, C, L, AD, Q);
1372    input D, C, L, AD;
1373    output reg Q;
1374    always @(posedge C or negedge L) begin
1375        if (L == 0)
1376            Q <= AD;
1377        else
1378            Q <= D;
1379    end
1380endmodule
yosys> help $_ALDFF_PP_

A positive edge D-type flip-flop with positive polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 1 a  | a
                d / - -  | d
                - - - -  | q
Simulation model (verilog)
Listing 280 simcells.v
1395module \$_ALDFF_PP_ (D, C, L, AD, Q);
1396    input D, C, L, AD;
1397    output reg Q;
1398    always @(posedge C or posedge L) begin
1399        if (L == 1)
1400            Q <= AD;
1401        else
1402            Q <= D;
1403    end
1404endmodule
yosys> help $_DFFE_NN0N_

A negative edge D-type flip-flop with negative polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 281 simcells.v
924module \$_DFFE_NN0N_ (D, C, R, E, Q);
925    input D, C, R, E;
926    output reg Q;
927    always @(negedge C or negedge R) begin
928        if (R == 0)
929            Q <= 0;
930        else if (E == 0)
931            Q <= D;
932    end
933endmodule
yosys> help $_DFFE_NN0P_

A negative edge D-type flip-flop with negative polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 282 simcells.v
949module \$_DFFE_NN0P_ (D, C, R, E, Q);
950    input D, C, R, E;
951    output reg Q;
952    always @(negedge C or negedge R) begin
953        if (R == 0)
954            Q <= 0;
955        else if (E == 1)
956            Q <= D;
957    end
958endmodule
yosys> help $_DFFE_NN1N_

A negative edge D-type flip-flop with negative polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 283 simcells.v
974module \$_DFFE_NN1N_ (D, C, R, E, Q);
975    input D, C, R, E;
976    output reg Q;
977    always @(negedge C or negedge R) begin
978        if (R == 0)
979            Q <= 1;
980        else if (E == 0)
981            Q <= D;
982    end
983endmodule
yosys> help $_DFFE_NN1P_

A negative edge D-type flip-flop with negative polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 284 simcells.v
 999module \$_DFFE_NN1P_ (D, C, R, E, Q);
1000    input D, C, R, E;
1001    output reg Q;
1002    always @(negedge C or negedge R) begin
1003        if (R == 0)
1004            Q <= 1;
1005        else if (E == 1)
1006            Q <= D;
1007    end
1008endmodule
yosys> help $_DFFE_NN_

A negative edge D-type flip-flop with negative polarity enable.

Truth table:    D C E | Q
               -------+---
                d \ 0 | d
                - - - | q
Simulation model (verilog)
Listing 285 simcells.v
650module \$_DFFE_NN_ (D, C, E, Q);
651    input D, C, E;
652    output reg Q;
653    always @(negedge C) begin
654        if (!E) Q <= D;
655    end
656endmodule
yosys> help $_DFFE_NP0N_

A negative edge D-type flip-flop with positive polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 286 simcells.v
1024module \$_DFFE_NP0N_ (D, C, R, E, Q);
1025    input D, C, R, E;
1026    output reg Q;
1027    always @(negedge C or posedge R) begin
1028        if (R == 1)
1029            Q <= 0;
1030        else if (E == 0)
1031            Q <= D;
1032    end
1033endmodule
yosys> help $_DFFE_NP0P_

A negative edge D-type flip-flop with positive polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 287 simcells.v
1049module \$_DFFE_NP0P_ (D, C, R, E, Q);
1050    input D, C, R, E;
1051    output reg Q;
1052    always @(negedge C or posedge R) begin
1053        if (R == 1)
1054            Q <= 0;
1055        else if (E == 1)
1056            Q <= D;
1057    end
1058endmodule
yosys> help $_DFFE_NP1N_

A negative edge D-type flip-flop with positive polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 288 simcells.v
1074module \$_DFFE_NP1N_ (D, C, R, E, Q);
1075    input D, C, R, E;
1076    output reg Q;
1077    always @(negedge C or posedge R) begin
1078        if (R == 1)
1079            Q <= 1;
1080        else if (E == 0)
1081            Q <= D;
1082    end
1083endmodule
yosys> help $_DFFE_NP1P_

A negative edge D-type flip-flop with positive polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 289 simcells.v
1099module \$_DFFE_NP1P_ (D, C, R, E, Q);
1100    input D, C, R, E;
1101    output reg Q;
1102    always @(negedge C or posedge R) begin
1103        if (R == 1)
1104            Q <= 1;
1105        else if (E == 1)
1106            Q <= D;
1107    end
1108endmodule
yosys> help $_DFFE_NP_

A negative edge D-type flip-flop with positive polarity enable.

Truth table:    D C E | Q
               -------+---
                d \ 1 | d
                - - - | q
Simulation model (verilog)
Listing 290 simcells.v
670module \$_DFFE_NP_ (D, C, E, Q);
671    input D, C, E;
672    output reg Q;
673    always @(negedge C) begin
674        if (E) Q <= D;
675    end
676endmodule
yosys> help $_DFFE_PN0N_

A positive edge D-type flip-flop with negative polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 291 simcells.v
1124module \$_DFFE_PN0N_ (D, C, R, E, Q);
1125    input D, C, R, E;
1126    output reg Q;
1127    always @(posedge C or negedge R) begin
1128        if (R == 0)
1129            Q <= 0;
1130        else if (E == 0)
1131            Q <= D;
1132    end
1133endmodule
yosys> help $_DFFE_PN0P_

A positive edge D-type flip-flop with negative polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 292 simcells.v
1149module \$_DFFE_PN0P_ (D, C, R, E, Q);
1150    input D, C, R, E;
1151    output reg Q;
1152    always @(posedge C or negedge R) begin
1153        if (R == 0)
1154            Q <= 0;
1155        else if (E == 1)
1156            Q <= D;
1157    end
1158endmodule
yosys> help $_DFFE_PN1N_

A positive edge D-type flip-flop with negative polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 293 simcells.v
1174module \$_DFFE_PN1N_ (D, C, R, E, Q);
1175    input D, C, R, E;
1176    output reg Q;
1177    always @(posedge C or negedge R) begin
1178        if (R == 0)
1179            Q <= 1;
1180        else if (E == 0)
1181            Q <= D;
1182    end
1183endmodule
yosys> help $_DFFE_PN1P_

A positive edge D-type flip-flop with negative polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 294 simcells.v
1199module \$_DFFE_PN1P_ (D, C, R, E, Q);
1200    input D, C, R, E;
1201    output reg Q;
1202    always @(posedge C or negedge R) begin
1203        if (R == 0)
1204            Q <= 1;
1205        else if (E == 1)
1206            Q <= D;
1207    end
1208endmodule
yosys> help $_DFFE_PN_

A positive edge D-type flip-flop with negative polarity enable.

Truth table:    D C E | Q
               -------+---
                d / 0 | d
                - - - | q
Simulation model (verilog)
Listing 295 simcells.v
690module \$_DFFE_PN_ (D, C, E, Q);
691    input D, C, E;
692    output reg Q;
693    always @(posedge C) begin
694        if (!E) Q <= D;
695    end
696endmodule
yosys> help $_DFFE_PP0N_

A positive edge D-type flip-flop with positive polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 296 simcells.v
1224module \$_DFFE_PP0N_ (D, C, R, E, Q);
1225    input D, C, R, E;
1226    output reg Q;
1227    always @(posedge C or posedge R) begin
1228        if (R == 1)
1229            Q <= 0;
1230        else if (E == 0)
1231            Q <= D;
1232    end
1233endmodule
yosys> help $_DFFE_PP0P_

A positive edge D-type flip-flop with positive polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 297 simcells.v
1249module \$_DFFE_PP0P_ (D, C, R, E, Q);
1250    input D, C, R, E;
1251    output reg Q;
1252    always @(posedge C or posedge R) begin
1253        if (R == 1)
1254            Q <= 0;
1255        else if (E == 1)
1256            Q <= D;
1257    end
1258endmodule
yosys> help $_DFFE_PP1N_

A positive edge D-type flip-flop with positive polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 298 simcells.v
1274module \$_DFFE_PP1N_ (D, C, R, E, Q);
1275    input D, C, R, E;
1276    output reg Q;
1277    always @(posedge C or posedge R) begin
1278        if (R == 1)
1279            Q <= 1;
1280        else if (E == 0)
1281            Q <= D;
1282    end
1283endmodule
yosys> help $_DFFE_PP1P_

A positive edge D-type flip-flop with positive polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 299 simcells.v
1299module \$_DFFE_PP1P_ (D, C, R, E, Q);
1300    input D, C, R, E;
1301    output reg Q;
1302    always @(posedge C or posedge R) begin
1303        if (R == 1)
1304            Q <= 1;
1305        else if (E == 1)
1306            Q <= D;
1307    end
1308endmodule
yosys> help $_DFFE_PP_

A positive edge D-type flip-flop with positive polarity enable.

Truth table:    D C E | Q
               -------+---
                d / 1 | d
                - - - | q
Simulation model (verilog)
Listing 300 simcells.v
710module \$_DFFE_PP_ (D, C, E, Q);
711    input D, C, E;
712    output reg Q;
713    always @(posedge C) begin
714        if (E) Q <= D;
715    end
716endmodule
yosys> help $_DFFSRE_NNNN_

A negative edge D-type flip-flop with negative polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 0 - - | x
                - - 0 - - | 0
                - 0 - - - | 1
                \ - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 301 simcells.v
1854module \$_DFFSRE_NNNN_ (C, S, R, E, D, Q);
1855    input C, S, R, E, D;
1856    output reg Q;
1857    always @(negedge C, negedge S, negedge R) begin
1858        if (R == 0)
1859            Q <= 0;
1860        else if (S == 0)
1861            Q <= 1;
1862            else if (E == 0)
1863            Q <= D;
1864    end
1865endmodule
yosys> help $_DFFSRE_NNNP_

A negative edge D-type flip-flop with negative polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 0 - - | x
                - - 0 - - | 0
                - 0 - - - | 1
                \ - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 302 simcells.v
1883module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
1884    input C, S, R, E, D;
1885    output reg Q;
1886    always @(negedge C, negedge S, negedge R) begin
1887        if (R == 0)
1888            Q <= 0;
1889        else if (S == 0)
1890            Q <= 1;
1891            else if (E == 1)
1892            Q <= D;
1893    end
1894endmodule
yosys> help $_DFFSRE_NNPN_

A negative edge D-type flip-flop with negative polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 1 - - | x
                - - 1 - - | 0
                - 0 - - - | 1
                \ - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 303 simcells.v
1912module \$_DFFSRE_NNPN_ (C, S, R, E, D, Q);
1913    input C, S, R, E, D;
1914    output reg Q;
1915    always @(negedge C, negedge S, posedge R) begin
1916        if (R == 1)
1917            Q <= 0;
1918        else if (S == 0)
1919            Q <= 1;
1920            else if (E == 0)
1921            Q <= D;
1922    end
1923endmodule
yosys> help $_DFFSRE_NNPP_

A negative edge D-type flip-flop with negative polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 1 - - | x
                - - 1 - - | 0
                - 0 - - - | 1
                \ - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 304 simcells.v
1941module \$_DFFSRE_NNPP_ (C, S, R, E, D, Q);
1942    input C, S, R, E, D;
1943    output reg Q;
1944    always @(negedge C, negedge S, posedge R) begin
1945        if (R == 1)
1946            Q <= 0;
1947        else if (S == 0)
1948            Q <= 1;
1949            else if (E == 1)
1950            Q <= D;
1951    end
1952endmodule
yosys> help $_DFFSRE_NPNN_

A negative edge D-type flip-flop with positive polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 0 - - | x
                - - 0 - - | 0
                - 1 - - - | 1
                \ - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 305 simcells.v
1970module \$_DFFSRE_NPNN_ (C, S, R, E, D, Q);
1971    input C, S, R, E, D;
1972    output reg Q;
1973    always @(negedge C, posedge S, negedge R) begin
1974        if (R == 0)
1975            Q <= 0;
1976        else if (S == 1)
1977            Q <= 1;
1978            else if (E == 0)
1979            Q <= D;
1980    end
1981endmodule
yosys> help $_DFFSRE_NPNP_

A negative edge D-type flip-flop with positive polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 0 - - | x
                - - 0 - - | 0
                - 1 - - - | 1
                \ - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 306 simcells.v
1999module \$_DFFSRE_NPNP_ (C, S, R, E, D, Q);
2000    input C, S, R, E, D;
2001    output reg Q;
2002    always @(negedge C, posedge S, negedge R) begin
2003        if (R == 0)
2004            Q <= 0;
2005        else if (S == 1)
2006            Q <= 1;
2007            else if (E == 1)
2008            Q <= D;
2009    end
2010endmodule
yosys> help $_DFFSRE_NPPN_

A negative edge D-type flip-flop with positive polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 1 - - | x
                - - 1 - - | 0
                - 1 - - - | 1
                \ - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 307 simcells.v
2028module \$_DFFSRE_NPPN_ (C, S, R, E, D, Q);
2029    input C, S, R, E, D;
2030    output reg Q;
2031    always @(negedge C, posedge S, posedge R) begin
2032        if (R == 1)
2033            Q <= 0;
2034        else if (S == 1)
2035            Q <= 1;
2036            else if (E == 0)
2037            Q <= D;
2038    end
2039endmodule
yosys> help $_DFFSRE_NPPP_

A negative edge D-type flip-flop with positive polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 1 - - | x
                - - 1 - - | 0
                - 1 - - - | 1
                \ - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 308 simcells.v
2057module \$_DFFSRE_NPPP_ (C, S, R, E, D, Q);
2058    input C, S, R, E, D;
2059    output reg Q;
2060    always @(negedge C, posedge S, posedge R) begin
2061        if (R == 1)
2062            Q <= 0;
2063        else if (S == 1)
2064            Q <= 1;
2065            else if (E == 1)
2066            Q <= D;
2067    end
2068endmodule
yosys> help $_DFFSRE_PNNN_

A positive edge D-type flip-flop with negative polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 0 - - | x
                - - 0 - - | 0
                - 0 - - - | 1
                / - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 309 simcells.v
2086module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
2087    input C, S, R, E, D;
2088    output reg Q;
2089    always @(posedge C, negedge S, negedge R) begin
2090        if (R == 0)
2091            Q <= 0;
2092        else if (S == 0)
2093            Q <= 1;
2094            else if (E == 0)
2095            Q <= D;
2096    end
2097endmodule
yosys> help $_DFFSRE_PNNP_

A positive edge D-type flip-flop with negative polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 0 - - | x
                - - 0 - - | 0
                - 0 - - - | 1
                / - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 310 simcells.v
2115module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
2116    input C, S, R, E, D;
2117    output reg Q;
2118    always @(posedge C, negedge S, negedge R) begin
2119        if (R == 0)
2120            Q <= 0;
2121        else if (S == 0)
2122            Q <= 1;
2123            else if (E == 1)
2124            Q <= D;
2125    end
2126endmodule
yosys> help $_DFFSRE_PNPN_

A positive edge D-type flip-flop with negative polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 1 - - | x
                - - 1 - - | 0
                - 0 - - - | 1
                / - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 311 simcells.v
2144module \$_DFFSRE_PNPN_ (C, S, R, E, D, Q);
2145    input C, S, R, E, D;
2146    output reg Q;
2147    always @(posedge C, negedge S, posedge R) begin
2148        if (R == 1)
2149            Q <= 0;
2150        else if (S == 0)
2151            Q <= 1;
2152            else if (E == 0)
2153            Q <= D;
2154    end
2155endmodule
yosys> help $_DFFSRE_PNPP_

A positive edge D-type flip-flop with negative polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 0 1 - - | x
                - - 1 - - | 0
                - 0 - - - | 1
                / - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 312 simcells.v
2173module \$_DFFSRE_PNPP_ (C, S, R, E, D, Q);
2174    input C, S, R, E, D;
2175    output reg Q;
2176    always @(posedge C, negedge S, posedge R) begin
2177        if (R == 1)
2178            Q <= 0;
2179        else if (S == 0)
2180            Q <= 1;
2181            else if (E == 1)
2182            Q <= D;
2183    end
2184endmodule
yosys> help $_DFFSRE_PPNN_

A positive edge D-type flip-flop with positive polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 0 - - | x
                - - 0 - - | 0
                - 1 - - - | 1
                / - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 313 simcells.v
2202module \$_DFFSRE_PPNN_ (C, S, R, E, D, Q);
2203    input C, S, R, E, D;
2204    output reg Q;
2205    always @(posedge C, posedge S, negedge R) begin
2206        if (R == 0)
2207            Q <= 0;
2208        else if (S == 1)
2209            Q <= 1;
2210            else if (E == 0)
2211            Q <= D;
2212    end
2213endmodule
yosys> help $_DFFSRE_PPNP_

A positive edge D-type flip-flop with positive polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 0 - - | x
                - - 0 - - | 0
                - 1 - - - | 1
                / - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 314 simcells.v
2231module \$_DFFSRE_PPNP_ (C, S, R, E, D, Q);
2232    input C, S, R, E, D;
2233    output reg Q;
2234    always @(posedge C, posedge S, negedge R) begin
2235        if (R == 0)
2236            Q <= 0;
2237        else if (S == 1)
2238            Q <= 1;
2239            else if (E == 1)
2240            Q <= D;
2241    end
2242endmodule
yosys> help $_DFFSRE_PPPN_

A positive edge D-type flip-flop with positive polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 1 - - | x
                - - 1 - - | 0
                - 1 - - - | 1
                / - - 0 d | d
                - - - - - | q
Simulation model (verilog)
Listing 315 simcells.v
2260module \$_DFFSRE_PPPN_ (C, S, R, E, D, Q);
2261    input C, S, R, E, D;
2262    output reg Q;
2263    always @(posedge C, posedge S, posedge R) begin
2264        if (R == 1)
2265            Q <= 0;
2266        else if (S == 1)
2267            Q <= 1;
2268            else if (E == 0)
2269            Q <= D;
2270    end
2271endmodule
yosys> help $_DFFSRE_PPPP_

A positive edge D-type flip-flop with positive polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - 1 1 - - | x
                - - 1 - - | 0
                - 1 - - - | 1
                / - - 1 d | d
                - - - - - | q
Simulation model (verilog)
Listing 316 simcells.v
2289module \$_DFFSRE_PPPP_ (C, S, R, E, D, Q);
2290    input C, S, R, E, D;
2291    output reg Q;
2292    always @(posedge C, posedge S, posedge R) begin
2293        if (R == 1)
2294            Q <= 0;
2295        else if (S == 1)
2296            Q <= 1;
2297            else if (E == 1)
2298            Q <= D;
2299    end
2300endmodule
yosys> help $_DFFSR_NNN_

A negative edge D-type flip-flop with negative polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 0 0 - | x
                - - 0 - | 0
                - 0 - - | 1
                \ - - d | d
                - - - - | q
Simulation model (verilog)
Listing 317 simcells.v
1622module \$_DFFSR_NNN_ (C, S, R, D, Q);
1623    input C, S, R, D;
1624    output reg Q;
1625    always @(negedge C, negedge S, negedge R) begin
1626        if (R == 0)
1627            Q <= 0;
1628        else if (S == 0)
1629            Q <= 1;
1630        else
1631            Q <= D;
1632    end
1633endmodule
yosys> help $_DFFSR_NNP_

A negative edge D-type flip-flop with negative polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 0 1 - | x
                - - 1 - | 0
                - 0 - - | 1
                \ - - d | d
                - - - - | q
Simulation model (verilog)
Listing 318 simcells.v
1651module \$_DFFSR_NNP_ (C, S, R, D, Q);
1652    input C, S, R, D;
1653    output reg Q;
1654    always @(negedge C, negedge S, posedge R) begin
1655        if (R == 1)
1656            Q <= 0;
1657        else if (S == 0)
1658            Q <= 1;
1659        else
1660            Q <= D;
1661    end
1662endmodule
yosys> help $_DFFSR_NPN_

A negative edge D-type flip-flop with positive polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 1 0 - | x
                - - 0 - | 0
                - 1 - - | 1
                \ - - d | d
                - - - - | q
Simulation model (verilog)
Listing 319 simcells.v
1680module \$_DFFSR_NPN_ (C, S, R, D, Q);
1681    input C, S, R, D;
1682    output reg Q;
1683    always @(negedge C, posedge S, negedge R) begin
1684        if (R == 0)
1685            Q <= 0;
1686        else if (S == 1)
1687            Q <= 1;
1688        else
1689            Q <= D;
1690    end
1691endmodule
yosys> help $_DFFSR_NPP_

A negative edge D-type flip-flop with positive polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 1 1 - | x
                - - 1 - | 0
                - 1 - - | 1
                \ - - d | d
                - - - - | q
Simulation model (verilog)
Listing 320 simcells.v
1709module \$_DFFSR_NPP_ (C, S, R, D, Q);
1710    input C, S, R, D;
1711    output reg Q;
1712    always @(negedge C, posedge S, posedge R) begin
1713        if (R == 1)
1714            Q <= 0;
1715        else if (S == 1)
1716            Q <= 1;
1717        else
1718            Q <= D;
1719    end
1720endmodule
yosys> help $_DFFSR_PNN_

A positive edge D-type flip-flop with negative polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 0 0 - | x
                - - 0 - | 0
                - 0 - - | 1
                / - - d | d
                - - - - | q
Simulation model (verilog)
Listing 321 simcells.v
1738module \$_DFFSR_PNN_ (C, S, R, D, Q);
1739    input C, S, R, D;
1740    output reg Q;
1741    always @(posedge C, negedge S, negedge R) begin
1742        if (R == 0)
1743            Q <= 0;
1744        else if (S == 0)
1745            Q <= 1;
1746        else
1747            Q <= D;
1748    end
1749endmodule
yosys> help $_DFFSR_PNP_

A positive edge D-type flip-flop with negative polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 0 1 - | x
                - - 1 - | 0
                - 0 - - | 1
                / - - d | d
                - - - - | q
Simulation model (verilog)
Listing 322 simcells.v
1767module \$_DFFSR_PNP_ (C, S, R, D, Q);
1768    input C, S, R, D;
1769    output reg Q;
1770    always @(posedge C, negedge S, posedge R) begin
1771        if (R == 1)
1772            Q <= 0;
1773        else if (S == 0)
1774            Q <= 1;
1775        else
1776            Q <= D;
1777    end
1778endmodule
yosys> help $_DFFSR_PPN_

A positive edge D-type flip-flop with positive polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 1 0 - | x
                - - 0 - | 0
                - 1 - - | 1
                / - - d | d
                - - - - | q
Simulation model (verilog)
Listing 323 simcells.v
1796module \$_DFFSR_PPN_ (C, S, R, D, Q);
1797    input C, S, R, D;
1798    output reg Q;
1799    always @(posedge C, posedge S, negedge R) begin
1800        if (R == 0)
1801            Q <= 0;
1802        else if (S == 1)
1803            Q <= 1;
1804        else
1805            Q <= D;
1806    end
1807endmodule
yosys> help $_DFFSR_PPP_

A positive edge D-type flip-flop with positive polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - 1 1 - | x
                - - 1 - | 0
                - 1 - - | 1
                / - - d | d
                - - - - | q
Simulation model (verilog)
Listing 324 simcells.v
1825module \$_DFFSR_PPP_ (C, S, R, D, Q);
1826    input C, S, R, D;
1827    output reg Q;
1828    always @(posedge C, posedge S, posedge R) begin
1829        if (R == 1)
1830            Q <= 0;
1831        else if (S == 1)
1832            Q <= 1;
1833        else
1834            Q <= D;
1835    end
1836endmodule
yosys> help $_DFF_NN0_

A negative edge D-type flip-flop with negative polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 0 | 0
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 325 simcells.v
731module \$_DFF_NN0_ (D, C, R, Q);
732    input D, C, R;
733    output reg Q;
734    always @(negedge C or negedge R) begin
735        if (R == 0)
736            Q <= 0;
737        else
738            Q <= D;
739    end
740endmodule
yosys> help $_DFF_NN1_

A negative edge D-type flip-flop with negative polarity set.

Truth table:    D C R | Q
               -------+---
                - - 0 | 1
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 326 simcells.v
755module \$_DFF_NN1_ (D, C, R, Q);
756    input D, C, R;
757    output reg Q;
758    always @(negedge C or negedge R) begin
759        if (R == 0)
760            Q <= 1;
761        else
762            Q <= D;
763    end
764endmodule
yosys> help $_DFF_NP0_

A negative edge D-type flip-flop with positive polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 1 | 0
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 327 simcells.v
779module \$_DFF_NP0_ (D, C, R, Q);
780    input D, C, R;
781    output reg Q;
782    always @(negedge C or posedge R) begin
783        if (R == 1)
784            Q <= 0;
785        else
786            Q <= D;
787    end
788endmodule
yosys> help $_DFF_NP1_

A negative edge D-type flip-flop with positive polarity set.

Truth table:    D C R | Q
               -------+---
                - - 1 | 1
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 328 simcells.v
803module \$_DFF_NP1_ (D, C, R, Q);
804    input D, C, R;
805    output reg Q;
806    always @(negedge C or posedge R) begin
807        if (R == 1)
808            Q <= 1;
809        else
810            Q <= D;
811    end
812endmodule
yosys> help $_DFF_N_

A negative edge D-type flip-flop.

Truth table:    D C | Q
               -----+---
                d \ | d
                - - | q
Simulation model (verilog)
Listing 329 simcells.v
610module \$_DFF_N_ (D, C, Q);
611    input D, C;
612    output reg Q;
613    always @(negedge C) begin
614        Q <= D;
615    end
616endmodule
yosys> help $_DFF_PN0_

A positive edge D-type flip-flop with negative polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 0 | 0
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 330 simcells.v
827module \$_DFF_PN0_ (D, C, R, Q);
828    input D, C, R;
829    output reg Q;
830    always @(posedge C or negedge R) begin
831        if (R == 0)
832            Q <= 0;
833        else
834            Q <= D;
835    end
836endmodule
yosys> help $_DFF_PN1_

A positive edge D-type flip-flop with negative polarity set.

Truth table:    D C R | Q
               -------+---
                - - 0 | 1
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 331 simcells.v
851module \$_DFF_PN1_ (D, C, R, Q);
852    input D, C, R;
853    output reg Q;
854    always @(posedge C or negedge R) begin
855        if (R == 0)
856            Q <= 1;
857        else
858            Q <= D;
859    end
860endmodule
yosys> help $_DFF_PP0_

A positive edge D-type flip-flop with positive polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 1 | 0
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 332 simcells.v
875module \$_DFF_PP0_ (D, C, R, Q);
876    input D, C, R;
877    output reg Q;
878    always @(posedge C or posedge R) begin
879        if (R == 1)
880            Q <= 0;
881        else
882            Q <= D;
883    end
884endmodule
yosys> help $_DFF_PP1_

A positive edge D-type flip-flop with positive polarity set.

Truth table:    D C R | Q
               -------+---
                - - 1 | 1
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 333 simcells.v
899module \$_DFF_PP1_ (D, C, R, Q);
900    input D, C, R;
901    output reg Q;
902    always @(posedge C or posedge R) begin
903        if (R == 1)
904            Q <= 1;
905        else
906            Q <= D;
907    end
908endmodule
yosys> help $_DFF_P_

A positive edge D-type flip-flop.

Truth table:    D C | Q
               -----+---
                d / | d
                - - | q
Simulation model (verilog)
Listing 334 simcells.v
630module \$_DFF_P_ (D, C, Q);
631    input D, C;
632    output reg Q;
633    always @(posedge C) begin
634        Q <= D;
635    end
636endmodule
yosys> help $_FF_

A D-type flip-flop that is clocked from the implicit global clock. (This cell type is usually only used in netlists for formal verification.)

Simulation model (verilog)
Listing 335 simcells.v
589module \$_FF_ (D, Q);
590    input D;
591    output reg Q;
592    always @($global_clock) begin
593        Q <= D;
594    end
595endmodule
yosys> help $_SDFFCE_NN0N_

A negative edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 0 | 0
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 336 simcells.v
2908module \$_SDFFCE_NN0N_ (D, C, R, E, Q);
2909    input D, C, R, E;
2910    output reg Q;
2911    always @(negedge C) begin
2912        if (E == 0) begin
2913            if (R == 0)
2914                Q <= 0;
2915            else
2916                Q <= D;
2917        end
2918    end
2919endmodule
yosys> help $_SDFFCE_NN0P_

A negative edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 1 | 0
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 337 simcells.v
2935module \$_SDFFCE_NN0P_ (D, C, R, E, Q);
2936    input D, C, R, E;
2937    output reg Q;
2938    always @(negedge C) begin
2939        if (E == 1) begin
2940            if (R == 0)
2941                Q <= 0;
2942            else
2943                Q <= D;
2944        end
2945    end
2946endmodule
yosys> help $_SDFFCE_NN1N_

A negative edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 0 | 1
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 338 simcells.v
2962module \$_SDFFCE_NN1N_ (D, C, R, E, Q);
2963    input D, C, R, E;
2964    output reg Q;
2965    always @(negedge C) begin
2966        if (E == 0) begin
2967            if (R == 0)
2968                Q <= 1;
2969            else
2970                Q <= D;
2971        end
2972    end
2973endmodule
yosys> help $_SDFFCE_NN1P_

A negative edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 1 | 1
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 339 simcells.v
2989module \$_SDFFCE_NN1P_ (D, C, R, E, Q);
2990    input D, C, R, E;
2991    output reg Q;
2992    always @(negedge C) begin
2993        if (E == 1) begin
2994            if (R == 0)
2995                Q <= 1;
2996            else
2997                Q <= D;
2998        end
2999    end
3000endmodule
yosys> help $_SDFFCE_NP0N_

A negative edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 0 | 0
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 340 simcells.v
3016module \$_SDFFCE_NP0N_ (D, C, R, E, Q);
3017    input D, C, R, E;
3018    output reg Q;
3019    always @(negedge C) begin
3020        if (E == 0) begin
3021            if (R == 1)
3022                Q <= 0;
3023            else
3024                Q <= D;
3025        end
3026    end
3027endmodule
yosys> help $_SDFFCE_NP0P_

A negative edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 1 | 0
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 341 simcells.v
3043module \$_SDFFCE_NP0P_ (D, C, R, E, Q);
3044    input D, C, R, E;
3045    output reg Q;
3046    always @(negedge C) begin
3047        if (E == 1) begin
3048            if (R == 1)
3049                Q <= 0;
3050            else
3051                Q <= D;
3052        end
3053    end
3054endmodule
yosys> help $_SDFFCE_NP1N_

A negative edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 0 | 1
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 342 simcells.v
3070module \$_SDFFCE_NP1N_ (D, C, R, E, Q);
3071    input D, C, R, E;
3072    output reg Q;
3073    always @(negedge C) begin
3074        if (E == 0) begin
3075            if (R == 1)
3076                Q <= 1;
3077            else
3078                Q <= D;
3079        end
3080    end
3081endmodule
yosys> help $_SDFFCE_NP1P_

A negative edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 1 | 1
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 343 simcells.v
3097module \$_SDFFCE_NP1P_ (D, C, R, E, Q);
3098    input D, C, R, E;
3099    output reg Q;
3100    always @(negedge C) begin
3101        if (E == 1) begin
3102            if (R == 1)
3103                Q <= 1;
3104            else
3105                Q <= D;
3106        end
3107    end
3108endmodule
yosys> help $_SDFFCE_PN0N_

A positive edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 0 | 0
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 344 simcells.v
3124module \$_SDFFCE_PN0N_ (D, C, R, E, Q);
3125    input D, C, R, E;
3126    output reg Q;
3127    always @(posedge C) begin
3128        if (E == 0) begin
3129            if (R == 0)
3130                Q <= 0;
3131            else
3132                Q <= D;
3133        end
3134    end
3135endmodule
yosys> help $_SDFFCE_PN0P_

A positive edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 1 | 0
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 345 simcells.v
3151module \$_SDFFCE_PN0P_ (D, C, R, E, Q);
3152    input D, C, R, E;
3153    output reg Q;
3154    always @(posedge C) begin
3155        if (E == 1) begin
3156            if (R == 0)
3157                Q <= 0;
3158            else
3159                Q <= D;
3160        end
3161    end
3162endmodule
yosys> help $_SDFFCE_PN1N_

A positive edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 0 | 1
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 346 simcells.v
3178module \$_SDFFCE_PN1N_ (D, C, R, E, Q);
3179    input D, C, R, E;
3180    output reg Q;
3181    always @(posedge C) begin
3182        if (E == 0) begin
3183            if (R == 0)
3184                Q <= 1;
3185            else
3186                Q <= D;
3187        end
3188    end
3189endmodule
yosys> help $_SDFFCE_PN1P_

A positive edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 1 | 1
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 347 simcells.v
3205module \$_SDFFCE_PN1P_ (D, C, R, E, Q);
3206    input D, C, R, E;
3207    output reg Q;
3208    always @(posedge C) begin
3209        if (E == 1) begin
3210            if (R == 0)
3211                Q <= 1;
3212            else
3213                Q <= D;
3214        end
3215    end
3216endmodule
yosys> help $_SDFFCE_PP0N_

A positive edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 0 | 0
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 348 simcells.v
3232module \$_SDFFCE_PP0N_ (D, C, R, E, Q);
3233    input D, C, R, E;
3234    output reg Q;
3235    always @(posedge C) begin
3236        if (E == 0) begin
3237            if (R == 1)
3238                Q <= 0;
3239            else
3240                Q <= D;
3241        end
3242    end
3243endmodule
yosys> help $_SDFFCE_PP0P_

A positive edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 1 | 0
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 349 simcells.v
3259module \$_SDFFCE_PP0P_ (D, C, R, E, Q);
3260    input D, C, R, E;
3261    output reg Q;
3262    always @(posedge C) begin
3263        if (E == 1) begin
3264            if (R == 1)
3265                Q <= 0;
3266            else
3267                Q <= D;
3268        end
3269    end
3270endmodule
yosys> help $_SDFFCE_PP1N_

A positive edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 0 | 1
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 350 simcells.v
3286module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
3287    input D, C, R, E;
3288    output reg Q;
3289    always @(posedge C) begin
3290        if (E == 0) begin
3291            if (R == 1)
3292                Q <= 1;
3293            else
3294                Q <= D;
3295        end
3296    end
3297endmodule
yosys> help $_SDFFCE_PP1P_

A positive edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 1 | 1
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 351 simcells.v
3313module \$_SDFFCE_PP1P_ (D, C, R, E, Q);
3314    input D, C, R, E;
3315    output reg Q;
3316    always @(posedge C) begin
3317        if (E == 1) begin
3318            if (R == 1)
3319                Q <= 1;
3320            else
3321                Q <= D;
3322        end
3323    end
3324endmodule
yosys> help $_SDFFE_NN0N_

A negative edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 0
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 352 simcells.v
2508module \$_SDFFE_NN0N_ (D, C, R, E, Q);
2509    input D, C, R, E;
2510    output reg Q;
2511    always @(negedge C) begin
2512        if (R == 0)
2513            Q <= 0;
2514        else if (E == 0)
2515            Q <= D;
2516    end
2517endmodule
yosys> help $_SDFFE_NN0P_

A negative edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 0
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 353 simcells.v
2533module \$_SDFFE_NN0P_ (D, C, R, E, Q);
2534    input D, C, R, E;
2535    output reg Q;
2536    always @(negedge C) begin
2537        if (R == 0)
2538            Q <= 0;
2539        else if (E == 1)
2540            Q <= D;
2541    end
2542endmodule
yosys> help $_SDFFE_NN1N_

A negative edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 1
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 354 simcells.v
2558module \$_SDFFE_NN1N_ (D, C, R, E, Q);
2559    input D, C, R, E;
2560    output reg Q;
2561    always @(negedge C) begin
2562        if (R == 0)
2563            Q <= 1;
2564        else if (E == 0)
2565            Q <= D;
2566    end
2567endmodule
yosys> help $_SDFFE_NN1P_

A negative edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 1
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 355 simcells.v
2583module \$_SDFFE_NN1P_ (D, C, R, E, Q);
2584    input D, C, R, E;
2585    output reg Q;
2586    always @(negedge C) begin
2587        if (R == 0)
2588            Q <= 1;
2589        else if (E == 1)
2590            Q <= D;
2591    end
2592endmodule
yosys> help $_SDFFE_NP0N_

A negative edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 0
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 356 simcells.v
2608module \$_SDFFE_NP0N_ (D, C, R, E, Q);
2609    input D, C, R, E;
2610    output reg Q;
2611    always @(negedge C) begin
2612        if (R == 1)
2613            Q <= 0;
2614        else if (E == 0)
2615            Q <= D;
2616    end
2617endmodule
yosys> help $_SDFFE_NP0P_

A negative edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 0
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 357 simcells.v
2633module \$_SDFFE_NP0P_ (D, C, R, E, Q);
2634    input D, C, R, E;
2635    output reg Q;
2636    always @(negedge C) begin
2637        if (R == 1)
2638            Q <= 0;
2639        else if (E == 1)
2640            Q <= D;
2641    end
2642endmodule
yosys> help $_SDFFE_NP1N_

A negative edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 1
                d \ - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 358 simcells.v
2658module \$_SDFFE_NP1N_ (D, C, R, E, Q);
2659    input D, C, R, E;
2660    output reg Q;
2661    always @(negedge C) begin
2662        if (R == 1)
2663            Q <= 1;
2664        else if (E == 0)
2665            Q <= D;
2666    end
2667endmodule
yosys> help $_SDFFE_NP1P_

A negative edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 1
                d \ - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 359 simcells.v
2683module \$_SDFFE_NP1P_ (D, C, R, E, Q);
2684    input D, C, R, E;
2685    output reg Q;
2686    always @(negedge C) begin
2687        if (R == 1)
2688            Q <= 1;
2689        else if (E == 1)
2690            Q <= D;
2691    end
2692endmodule
yosys> help $_SDFFE_PN0N_

A positive edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 0
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 360 simcells.v
2708module \$_SDFFE_PN0N_ (D, C, R, E, Q);
2709    input D, C, R, E;
2710    output reg Q;
2711    always @(posedge C) begin
2712        if (R == 0)
2713            Q <= 0;
2714        else if (E == 0)
2715            Q <= D;
2716    end
2717endmodule
yosys> help $_SDFFE_PN0P_

A positive edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 0
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 361 simcells.v
2733module \$_SDFFE_PN0P_ (D, C, R, E, Q);
2734    input D, C, R, E;
2735    output reg Q;
2736    always @(posedge C) begin
2737        if (R == 0)
2738            Q <= 0;
2739        else if (E == 1)
2740            Q <= D;
2741    end
2742endmodule
yosys> help $_SDFFE_PN1N_

A positive edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 1
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 362 simcells.v
2758module \$_SDFFE_PN1N_ (D, C, R, E, Q);
2759    input D, C, R, E;
2760    output reg Q;
2761    always @(posedge C) begin
2762        if (R == 0)
2763            Q <= 1;
2764        else if (E == 0)
2765            Q <= D;
2766    end
2767endmodule
yosys> help $_SDFFE_PN1P_

A positive edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 1
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 363 simcells.v
2783module \$_SDFFE_PN1P_ (D, C, R, E, Q);
2784    input D, C, R, E;
2785    output reg Q;
2786    always @(posedge C) begin
2787        if (R == 0)
2788            Q <= 1;
2789        else if (E == 1)
2790            Q <= D;
2791    end
2792endmodule
yosys> help $_SDFFE_PP0N_

A positive edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 0
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 364 simcells.v
2808module \$_SDFFE_PP0N_ (D, C, R, E, Q);
2809    input D, C, R, E;
2810    output reg Q;
2811    always @(posedge C) begin
2812        if (R == 1)
2813            Q <= 0;
2814        else if (E == 0)
2815            Q <= D;
2816    end
2817endmodule
yosys> help $_SDFFE_PP0P_

A positive edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 0
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 365 simcells.v
2833module \$_SDFFE_PP0P_ (D, C, R, E, Q);
2834    input D, C, R, E;
2835    output reg Q;
2836    always @(posedge C) begin
2837        if (R == 1)
2838            Q <= 0;
2839        else if (E == 1)
2840            Q <= D;
2841    end
2842endmodule
yosys> help $_SDFFE_PP1N_

A positive edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 1
                d / - 0 | d
                - - - - | q
Simulation model (verilog)
Listing 366 simcells.v
2858module \$_SDFFE_PP1N_ (D, C, R, E, Q);
2859    input D, C, R, E;
2860    output reg Q;
2861    always @(posedge C) begin
2862        if (R == 1)
2863            Q <= 1;
2864        else if (E == 0)
2865            Q <= D;
2866    end
2867endmodule
yosys> help $_SDFFE_PP1P_

A positive edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 1
                d / - 1 | d
                - - - - | q
Simulation model (verilog)
Listing 367 simcells.v
2883module \$_SDFFE_PP1P_ (D, C, R, E, Q);
2884    input D, C, R, E;
2885    output reg Q;
2886    always @(posedge C) begin
2887        if (R == 1)
2888            Q <= 1;
2889        else if (E == 1)
2890            Q <= D;
2891    end
2892endmodule
yosys> help $_SDFF_NN0_

A negative edge D-type flip-flop with negative polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - \ 0 | 0
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 368 simcells.v
2315module \$_SDFF_NN0_ (D, C, R, Q);
2316    input D, C, R;
2317    output reg Q;
2318    always @(negedge C) begin
2319        if (R == 0)
2320            Q <= 0;
2321        else
2322            Q <= D;
2323    end
2324endmodule
yosys> help $_SDFF_NN1_

A negative edge D-type flip-flop with negative polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - \ 0 | 1
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 369 simcells.v
2339module \$_SDFF_NN1_ (D, C, R, Q);
2340    input D, C, R;
2341    output reg Q;
2342    always @(negedge C) begin
2343        if (R == 0)
2344            Q <= 1;
2345        else
2346            Q <= D;
2347    end
2348endmodule
yosys> help $_SDFF_NP0_

A negative edge D-type flip-flop with positive polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - \ 1 | 0
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 370 simcells.v
2363module \$_SDFF_NP0_ (D, C, R, Q);
2364    input D, C, R;
2365    output reg Q;
2366    always @(negedge C) begin
2367        if (R == 1)
2368            Q <= 0;
2369        else
2370            Q <= D;
2371    end
2372endmodule
yosys> help $_SDFF_NP1_

A negative edge D-type flip-flop with positive polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - \ 1 | 1
                d \ - | d
                - - - | q
Simulation model (verilog)
Listing 371 simcells.v
2387module \$_SDFF_NP1_ (D, C, R, Q);
2388    input D, C, R;
2389    output reg Q;
2390    always @(negedge C) begin
2391        if (R == 1)
2392            Q <= 1;
2393        else
2394            Q <= D;
2395    end
2396endmodule
yosys> help $_SDFF_PN0_

A positive edge D-type flip-flop with negative polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - / 0 | 0
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 372 simcells.v
2411module \$_SDFF_PN0_ (D, C, R, Q);
2412    input D, C, R;
2413    output reg Q;
2414    always @(posedge C) begin
2415        if (R == 0)
2416            Q <= 0;
2417        else
2418            Q <= D;
2419    end
2420endmodule
yosys> help $_SDFF_PN1_

A positive edge D-type flip-flop with negative polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - / 0 | 1
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 373 simcells.v
2435module \$_SDFF_PN1_ (D, C, R, Q);
2436    input D, C, R;
2437    output reg Q;
2438    always @(posedge C) begin
2439        if (R == 0)
2440            Q <= 1;
2441        else
2442            Q <= D;
2443    end
2444endmodule
yosys> help $_SDFF_PP0_

A positive edge D-type flip-flop with positive polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - / 1 | 0
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 374 simcells.v
2459module \$_SDFF_PP0_ (D, C, R, Q);
2460    input D, C, R;
2461    output reg Q;
2462    always @(posedge C) begin
2463        if (R == 1)
2464            Q <= 0;
2465        else
2466            Q <= D;
2467    end
2468endmodule
yosys> help $_SDFF_PP1_

A positive edge D-type flip-flop with positive polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - / 1 | 1
                d / - | d
                - - - | q
Simulation model (verilog)
Listing 375 simcells.v
2483module \$_SDFF_PP1_ (D, C, R, Q);
2484    input D, C, R;
2485    output reg Q;
2486    always @(posedge C) begin
2487        if (R == 1)
2488            Q <= 1;
2489        else
2490            Q <= D;
2491    end
2492endmodule