Registers

SR-type latches are represented by $sr cells. These cells have input ports SET and CLR and an output port Q. They have the following parameters:

WIDTH

The width of inputs SET and CLR and output Q.

SET_POLARITY

The set input bits are active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

CLR_POLARITY

The reset input bits are active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

Both set and reset inputs have separate bits for every output bit. When both the set and reset inputs of an $sr cell are active for a given bit index, the reset input takes precedence.

D-type flip-flops are represented by $dff cells. These cells have a clock port CLK, an input port D and an output port Q. The following parameters are available for $dff cells:

WIDTH

The width of input D and output Q.

CLK_POLARITY

Clock is active on the positive edge if this parameter has the value 1'b1 and on the negative edge if this parameter is 1'b0.

D-type flip-flops with asynchronous reset are represented by $adff cells. As the $dff cells they have CLK, D and Q ports. In addition they also have a single-bit ARST input port for the reset pin and the following additional two parameters:

ARST_POLARITY

The asynchronous reset is active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

ARST_VALUE

The state of Q will be set to this value when the reset is active.

Usually these cells are generated by the proc pass using the information in the designs RTLIL::Process objects.

D-type flip-flops with synchronous reset are represented by $sdff cells. As the $dff cells they have CLK, D and Q ports. In addition they also have a single-bit SRST input port for the reset pin and the following additional two parameters:

SRST_POLARITY

The synchronous reset is active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

SRST_VALUE

The state of Q will be set to this value when the reset is active.

Note that the $adff and $sdff cells can only be used when the reset value is constant.

D-type flip-flops with asynchronous load are represented by $aldff cells. As the $dff cells they have CLK, D and Q ports. In addition they also have a single-bit ALOAD input port for the async load enable pin, a AD input port with the same width as data for the async load data, and the following additional parameter:

ALOAD_POLARITY

The asynchronous load is active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

D-type flip-flops with asynchronous set and reset are represented by $dffsr cells. As the $dff cells they have CLK, D and Q ports. In addition they also have multi-bit SET and CLR input ports and the corresponding polarity parameters, like $sr cells. When both set and reset are active, the state and output is undefined.

D-type flip-flops with enable are represented by $dffe, $adffe, $aldffe, $dffsre, $sdffe, and $sdffce cells, which are enhanced variants of $dff, $adff, $aldff, $dffsr, $sdff (with reset over enable) and $sdff (with enable over reset) cells, respectively. They have the same ports and parameters as their base cell. In addition they also have a single-bit EN input port for the enable pin and the following parameter:

EN_POLARITY

The enable input is active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

D-type latches are represented by $dlatch cells. These cells have an enable port EN, an input port D, and an output port Q. The following parameters are available for $dlatch cells:

WIDTH

The width of input D and output Q.

EN_POLARITY

The enable input is active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

The latch is transparent when the EN input is active.

D-type latches with reset are represented by $adlatch cells. In addition to $dlatch ports and parameters, they also have a single-bit ARST input port for the reset pin and the following additional parameters:

ARST_POLARITY

The asynchronous reset is active-high if this parameter has the value 1'b1 and active-low if this parameter is 1'b0.

ARST_VALUE

The state of Q will be set to this value when the reset is active.

D-type latches with set and reset are represented by $dlatchsr cells. In addition to $dlatch ports and parameters, they also have multi-bit SET and CLR input ports and the corresponding polarity parameters, like $sr cells.

yosys> help $adff

Simulation model (verilog)

Listing 193 simlib.v

module \$adff (CLK, ARST, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter ARST_POLARITY = 1'b1;
    parameter ARST_VALUE = 0;

    input CLK, ARST;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;
    wire pos_arst = ARST == ARST_POLARITY;

    always @(posedge pos_clk, posedge pos_arst) begin
        if (pos_arst)
            Q <= ARST_VALUE;
        else
            Q <= D;
    end

endmodule

yosys> help $adffe

Simulation model (verilog)

Listing 194 simlib.v

module \$adffe (CLK, ARST, EN, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter EN_POLARITY = 1'b1;
    parameter ARST_POLARITY = 1'b1;
    parameter ARST_VALUE = 0;

    input CLK, ARST, EN;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;
    wire pos_arst = ARST == ARST_POLARITY;

    always @(posedge pos_clk, posedge pos_arst) begin
        if (pos_arst)
            Q <= ARST_VALUE;
        else if (EN == EN_POLARITY)
            Q <= D;
    end

endmodule

yosys> help $adlatch

Simulation model (verilog)

Listing 195 simlib.v

module \$adlatch (EN, ARST, D, Q);

    parameter WIDTH = 0;
    parameter EN_POLARITY = 1'b1;
    parameter ARST_POLARITY = 1'b1;
    parameter ARST_VALUE = 0;

    input EN, ARST;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;

    always @* begin
        if (ARST == ARST_POLARITY)
            Q = ARST_VALUE;
        else if (EN == EN_POLARITY)
            Q = D;
    end

endmodule

yosys> help $aldff

Simulation model (verilog)

Listing 196 simlib.v

module \$aldff (CLK, ALOAD, AD, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter ALOAD_POLARITY = 1'b1;

    input CLK, ALOAD;
    input [WIDTH-1:0] AD;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;
    wire pos_aload = ALOAD == ALOAD_POLARITY;

    always @(posedge pos_clk, posedge pos_aload) begin
        if (pos_aload)
            Q <= AD;
        else
            Q <= D;
    end

endmodule

yosys> help $aldffe

Simulation model (verilog)

Listing 197 simlib.v

module \$aldffe (CLK, ALOAD, AD, EN, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter EN_POLARITY = 1'b1;
    parameter ALOAD_POLARITY = 1'b1;

    input CLK, ALOAD, EN;
    input [WIDTH-1:0] D;
    input [WIDTH-1:0] AD;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;
    wire pos_aload = ALOAD == ALOAD_POLARITY;

    always @(posedge pos_clk, posedge pos_aload) begin
        if (pos_aload)
            Q <= AD;
        else if (EN == EN_POLARITY)
            Q <= D;
    end

endmodule

yosys> help $dff

Simulation model (verilog)

Listing 198 simlib.v

module \$dff (CLK, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;

    input CLK;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;

    always @(posedge pos_clk) begin
        Q <= D;
    end

endmodule

yosys> help $dffe

Simulation model (verilog)

Listing 199 simlib.v

module \$dffe (CLK, EN, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter EN_POLARITY = 1'b1;

    input CLK, EN;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;

    always @(posedge pos_clk) begin
        if (EN == EN_POLARITY) Q <= D;
    end

endmodule

yosys> help $dffsr

Simulation model (verilog)

Listing 200 simlib.v

module \$dffsr (CLK, SET, CLR, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter SET_POLARITY = 1'b1;
    parameter CLR_POLARITY = 1'b1;

    input CLK;
    input [WIDTH-1:0] SET, CLR, D;
    output reg [WIDTH-1:0] Q;

    wire pos_clk = CLK == CLK_POLARITY;
    wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
    wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;

    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i+1) begin:bitslices
            always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
                if (pos_clr[i])
                    Q[i] <= 0;
                else if (pos_set[i])
                    Q[i] <= 1;
                else
                    Q[i] <= D[i];
        end
    endgenerate

endmodule

yosys> help $dffsre

Simulation model (verilog)

Listing 201 simlib.v

module \$dffsre (CLK, SET, CLR, EN, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter SET_POLARITY = 1'b1;
    parameter CLR_POLARITY = 1'b1;
    parameter EN_POLARITY = 1'b1;

    input CLK, EN;
    input [WIDTH-1:0] SET, CLR, D;
    output reg [WIDTH-1:0] Q;

    wire pos_clk = CLK == CLK_POLARITY;
    wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
    wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;

    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i+1) begin:bitslices
            always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
                if (pos_clr[i])
                    Q[i] <= 0;
                else if (pos_set[i])
                    Q[i] <= 1;
                else if (EN == EN_POLARITY)
                    Q[i] <= D[i];
        end
    endgenerate

endmodule

yosys> help $dlatch

Simulation model (verilog)

Listing 202 simlib.v

module \$dlatch (EN, D, Q);

    parameter WIDTH = 0;
    parameter EN_POLARITY = 1'b1;

    input EN;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;

    always @* begin
        if (EN == EN_POLARITY)
            Q = D;
    end

endmodule

yosys> help $dlatchsr

Simulation model (verilog)

Listing 203 simlib.v

module \$dlatchsr (EN, SET, CLR, D, Q);

    parameter WIDTH = 0;
    parameter EN_POLARITY = 1'b1;
    parameter SET_POLARITY = 1'b1;
    parameter CLR_POLARITY = 1'b1;

    input EN;
    input [WIDTH-1:0] SET, CLR, D;
    output reg [WIDTH-1:0] Q;

    wire pos_en = EN == EN_POLARITY;
    wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
    wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;

    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i+1) begin:bitslices
            always @*
                if (pos_clr[i])
                    Q[i] = 0;
                else if (pos_set[i])
                    Q[i] = 1;
                else if (pos_en)
                    Q[i] = D[i];
        end
    endgenerate

endmodule

yosys> help $sdff

Simulation model (verilog)

Listing 204 simlib.v

module \$sdff (CLK, SRST, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter SRST_POLARITY = 1'b1;
    parameter SRST_VALUE = 0;

    input CLK, SRST;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;
    wire pos_srst = SRST == SRST_POLARITY;

    always @(posedge pos_clk) begin
        if (pos_srst)
            Q <= SRST_VALUE;
        else
            Q <= D;
    end

endmodule

yosys> help $sdffce

Simulation model (verilog)

Listing 205 simlib.v

module \$sdffce (CLK, SRST, EN, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter EN_POLARITY = 1'b1;
    parameter SRST_POLARITY = 1'b1;
    parameter SRST_VALUE = 0;

    input CLK, SRST, EN;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;
    wire pos_srst = SRST == SRST_POLARITY;

    always @(posedge pos_clk) begin
        if (EN == EN_POLARITY) begin
            if (pos_srst)
                Q <= SRST_VALUE;
            else
                Q <= D;
        end
    end

endmodule

yosys> help $sdffe

Simulation model (verilog)

Listing 206 simlib.v

module \$sdffe (CLK, SRST, EN, D, Q);

    parameter WIDTH = 0;
    parameter CLK_POLARITY = 1'b1;
    parameter EN_POLARITY = 1'b1;
    parameter SRST_POLARITY = 1'b1;
    parameter SRST_VALUE = 0;

    input CLK, SRST, EN;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;
    wire pos_clk = CLK == CLK_POLARITY;
    wire pos_srst = SRST == SRST_POLARITY;

    always @(posedge pos_clk) begin
        if (pos_srst)
            Q <= SRST_VALUE;
        else if (EN == EN_POLARITY)
            Q <= D;
    end

endmodule

yosys> help $sr

Simulation model (verilog)

Listing 207 simlib.v

module \$sr (SET, CLR, Q);

    parameter WIDTH = 0;
    parameter SET_POLARITY = 1'b1;
    parameter CLR_POLARITY = 1'b1;

    input [WIDTH-1:0] SET, CLR;
    output reg [WIDTH-1:0] Q;

    wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
    wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;

    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i+1) begin:bitslices
            always @*
                if (pos_clr[i])
                    Q[i] <= 0;
                else if (pos_set[i])
                    Q[i] <= 1;
        end
    endgenerate

endmodule