FABulous

synth_fabulous - FABulous synthesis script

yosys> help synth_fabulous

synth_fabulous [options]

This command runs synthesis for FPGA fabrics generated with FABulous. This command does not operate
on partly selected designs.

-top <module>

use the specified module as top module (default='top')

-auto-top

automatically determine the top of the design hierarchy

-json <file>

write the design to the specified JSON file. writing of an output file
is omitted if this parameter is not specified.

-lut <k>

perform synthesis for a k-LUT architecture (default 4).

-ff <cell_type_pattern> <init_values>

convert FFs to cell types via dfflegalize (can be specified multiple times).

-cells-map <cells_map>

map luts to corresponding cells.

-arith-map <arith_map>

mapping file for arithmetic operations.

-clkbuf-map <clkbuf_map>

insert clock buffers using clkbufmap and map to the specified Verilog file.

-multiplier-map <multiplier_map> <a_max> <b_max> <a_min> <b_min> <y_min>

convert multiplications to multiplier primitives and map to the specified Verilog file.

-extra-plib <primitive_library.v>

use the specified Verilog file for extra primitives (can be specified multiple
times).

-extra-map <techmap.v>

use the specified Verilog file for extra techmap rules (can be specified multiple
times).

-extra-mlibmap <memory_map.txt>

use the provided library convert memory into hardware supported memory (can be specified
multiple times).

-nofsm

do not run FSM optimization

-noalumacc

do not run 'alumacc' pass. i.e. keep arithmetic operators in
their direct form ($add, $sub, etc.).

-carry <none|ha>

carry mapping style (none, half-adders, ...) default=none

-noiopad

disable I/O buffer insertion (useful for hierarchical or
out-of-context flows).

-noflatten

do not flatten design after elaboration

-nordff

passed to 'memory'. prohibits merging of FFs into memory read ports

-noshare

do not run SAT-based resource sharing

-run <from_label>[:<to_label>]

only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.

-no-rw-check

marks all recognized read ports as "return don't-care value on
read/write collision" (same result as setting the no_rw_check
attribute on all memories).

-latches <info|warn|error>

select the behaviour for latches that cannot be mapped to a
dedicated hardware primitive and are implemented using LUTs
instead. 'error' (the default) aborts synthesis, 'warn' only
prints a warning, and 'info' permits them with an info-level message.

The following commands are executed by this synthesis command:
        read_verilog -lib <extra_plib.v>    (for each -extra-plib)

    begin:
        hierarchy -check
        proc -latches warn

    flatten:    (unless -noflatten)
        check
        flatten
        tribuf -logic
        deminout

    coarse:
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm          (unless -nofsm)
        opt
        wreduce
        peepopt
        opt_clean
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v     (if -lut)
        wreduce t:$mul
        techmap -map +/mul2dsp.v -map <multiplier_map> -D DSP_A_MAXWIDTH=<a_max> -D DSP_B_MAXWIDTH=<b_max> -D DSP_A_MINWIDTH=<a_min> -D DSP_B_MINWIDTH=<b_min> -D DSP_Y_MINWIDTH=<y_min> -D DSP_NAME=$__FABULOUS_MUL    (if -multiplier-map)
        select a:mul2dsp                  (if -multiplier-map)
        setattr -unset mul2dsp            (if -multiplier-map)
        opt_expr -fine                    (if -multiplier-map)
        wreduce                           (if -multiplier-map)
        select -clear                     (if -multiplier-map)
        chtype -set $mul t:$__soft_mul    (if -multiplier-map)
        alumacc      (unless -noalumacc)
        share        (unless -noshare)
        opt
        memory -nomap
        opt_clean

    map_memory:
        memory_libmap -lib <memory_map.txt>    (for each -extra-mlibmap)

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_arith:
        techmap -map <arith_map.v> -D ARITH_<carry>
        clean

    map_gates:
        opt -full
        techmap -map +/techmap.v
        opt -fast

    map_iopad:    (skip if -noiopad)
        opt -full
        iopadmap -bits -inpad $__FABULOUS_IBUF OUT:PAD -outpad $__FABULOUS_OBUF IN:PAD -toutpad $__FABULOUS_TBUF EN:IN:PAD -tinoutpad $__FABULOUS_IOBUF EN:OUT:IN:PAD

    map_ffs:
        dfflegalize -cell <cell_type_pattern> <init_values>...    (for each -ff)
        check -latchonly -assert    (only if -latches error, the default)
        opt_merge

    map_extra:
        techmap -map <extra_map.v>...    (for each -extra-map)
        simplemap
        clean

    map_luts:
        abc -lut 4 -dress
        clean

    map_cells:
        techmap -D LUT_K=<lut> -map <cells_map.v>
        clean

    map_clkbufs:
        clkbufmap -buf $__FABULOUS_GBUF OUT:IN    (if -clkbuf-map <clkbuf_map.v>)
        techmap -map <clkbuf_map.v>    (if -clkbuf-map <clkbuf_map.v>)

    check:
        hierarchy -check
        stat

    json:
        write_json <file-name>

Note

Help text automatically generated from techlibs/fabulous/synth_fabulous.cc:29