Wire cells

yosys> help $concat

Concatenation of inputs into a single output ( Y = {B, A} ).

Properties:

is_evaluable

Simulation model (verilog)

Listing 248 simlib.v

module \$concat (A, B, Y);

    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [A_WIDTH+B_WIDTH-1:0] Y;

    assign Y = {B, A};

endmodule

yosys> help $connect

Simulation model (verilog)

Listing 249 simlib.v

module \$connect (A, B);

    parameter WIDTH = 0;

    inout [WIDTH-1:0] A;
    inout [WIDTH-1:0] B;

    tran connect[WIDTH-1:0] (A, B);

endmodule

yosys> help $input_port

Simulation model (verilog)

Listing 250 simlib.v

module \$input_port (Y);

    parameter WIDTH = 0;

    inout [WIDTH-1:0] Y;

endmodule

yosys> help $slice

Properties:

is_evaluable

Simulation model (verilog)

Listing 251 simlib.v

module \$slice (A, Y);

    parameter OFFSET = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    assign Y = A >> OFFSET;

endmodule