Unary operators

All unary RTL cells have one input port A and one output port Y. They also have the following parameters:

A_SIGNED

Set to a non-zero value if the input A is signed and therefore should be sign-extended when needed.

A_WIDTH

The width of the input port A.

Y_WIDTH

The width of the output port Y.

Table 4 Cell types for unary operators with their corresponding Verilog expressions.

Verilog

Cell Type

Y = ~A

$not

Y = +A

$pos

Y = -A

$neg

Y = &A

$reduce_and

Y = |A

$reduce_or

Y = ^A

$reduce_xor

Y = ~^A

$reduce_xnor

Y = |A

$reduce_bool

Y = !A

$logic_not

For the unary cells that output a logical value ($reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool, $logic_not), when the Y_WIDTH parameter is greater than 1, the output is zero-extended, and only the least significant bit varies.

Note that $reduce_or and $reduce_bool generally represent the same logic function. But the read_verilog frontend will generate them in different situations. A $reduce_or cell is generated when the prefix | operator is being used. A $reduce_bool cell is generated when a bit vector is used as a condition in an if-statement or ?:-expression.

yosys> help $barrier

A coarse-grain buffer cell type that acts as a barrier for optimizations. Optimization passes are forbidden from rewriting patterns that include this cell (by merging, constant propagation etc) with the exception of opt_clean that can remove it if the output is unused.

Simulation model (verilog)
Listing 147 simlib.v
129module \$barrier (A, Y);
130
131    parameter WIDTH = 0;
132
133    input [WIDTH-1:0] A;
134    output [WIDTH-1:0] Y;
135
136    assign Y = A;
137
138endmodule
yosys> help $buf

A simple coarse-grain buffer cell type for the experimental buffered-normalized mode. Note this cell does’t get removed by ‘opt_clean’ and is not recommended for general use.

Properties:

is_evaluable

Simulation model (verilog)
Listing 148 simlib.v
106module \$buf (A, Y);
107
108    parameter WIDTH = 0;
109
110    input [WIDTH-1:0] A;
111    output [WIDTH-1:0] Y;
112
113    assign Y = A;
114
115endmodule
yosys> help $logic_not

A logical inverter. This corresponds to the Verilog unary prefix ‘!’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 149 simlib.v
1544module \$logic_not (A, Y);
1545
1546    parameter A_SIGNED = 0;
1547    parameter A_WIDTH = 0;
1548    parameter Y_WIDTH = 0;
1549
1550    input [A_WIDTH-1:0] A;
1551    output [Y_WIDTH-1:0] Y;
1552
1553    generate
1554        if (A_SIGNED) begin:BLOCK1
1555            assign Y = !$signed(A);
1556        end else begin:BLOCK2
1557            assign Y = !A;
1558        end
1559    endgenerate
1560
1561endmodule
yosys> help $neg

An arithmetic inverter. This corresponds to the Verilog unary prefix ‘-’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 150 simlib.v
149module \$neg (A, Y);
150
151    parameter A_SIGNED = 0;
152    parameter A_WIDTH = 0;
153    parameter Y_WIDTH = 0;
154
155    input [A_WIDTH-1:0] A;
156    output [Y_WIDTH-1:0] Y;
157
158    generate
159        if (A_SIGNED) begin:BLOCK1
160            assign Y = -$signed(A);
161        end else begin:BLOCK2
162            assign Y = -A;
163        end
164    endgenerate
165
166endmodule
yosys> help $not

Bit-wise inverter

This corresponds to the Verilog unary prefix ‘~’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 151 simlib.v
48module \$not (A, Y);
49
50    parameter A_SIGNED = 0;
51    parameter A_WIDTH = 0;
52    parameter Y_WIDTH = 0;
53
54    input [A_WIDTH-1:0] A;
55    output [Y_WIDTH-1:0] Y;
56
57    generate
58        if (A_SIGNED) begin:BLOCK1
59            assign Y = ~$signed(A);
60        end else begin:BLOCK2
61            assign Y = ~A;
62        end
63    endgenerate
64
65endmodule
yosys> help $pos

A buffer. This corresponds to the Verilog unary prefix ‘+’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 152 simlib.v
76module \$pos (A, Y);
77
78    parameter A_SIGNED = 0;
79    parameter A_WIDTH = 0;
80    parameter Y_WIDTH = 0;
81
82    input [A_WIDTH-1:0] A;
83    output [Y_WIDTH-1:0] Y;
84
85    generate
86        if (A_SIGNED) begin:BLOCK1
87            assign Y = $signed(A);
88        end else begin:BLOCK2
89            assign Y = A;
90        end
91    endgenerate
92
93endmodule
yosys> help $reduce_and

An AND reduction. This corresponds to the Verilog unary prefix ‘&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 153 simlib.v
301module \$reduce_and (A, Y);
302
303    parameter A_SIGNED = 0;
304    parameter A_WIDTH = 0;
305    parameter Y_WIDTH = 0;
306
307    input [A_WIDTH-1:0] A;
308    output [Y_WIDTH-1:0] Y;
309
310    generate
311        if (A_SIGNED) begin:BLOCK1
312            assign Y = &$signed(A);
313        end else begin:BLOCK2
314            assign Y = &A;
315        end
316    endgenerate
317
318endmodule
yosys> help $reduce_bool

An OR reduction. This cell type is used instead of $reduce_or when a signal is implicitly converted to a boolean signal, e.g. for operands of ‘&&’ and ‘||’.

Properties:

is_evaluable

Simulation model (verilog)
Listing 154 simlib.v
414module \$reduce_bool (A, Y);
415
416    parameter A_SIGNED = 0;
417    parameter A_WIDTH = 0;
418    parameter Y_WIDTH = 0;
419
420    input [A_WIDTH-1:0] A;
421    output [Y_WIDTH-1:0] Y;
422
423    generate
424        if (A_SIGNED) begin:BLOCK1
425            assign Y = !(!$signed(A));
426        end else begin:BLOCK2
427            assign Y = !(!A);
428        end
429    endgenerate
430
431endmodule
yosys> help $reduce_or

An OR reduction. This corresponds to the Verilog unary prefix ‘|’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 155 simlib.v
329module \$reduce_or (A, Y);
330
331    parameter A_SIGNED = 0;
332    parameter A_WIDTH = 0;
333    parameter Y_WIDTH = 0;
334
335    input [A_WIDTH-1:0] A;
336    output [Y_WIDTH-1:0] Y;
337
338    generate
339        if (A_SIGNED) begin:BLOCK1
340            assign Y = |$signed(A);
341        end else begin:BLOCK2
342            assign Y = |A;
343        end
344    endgenerate
345
346endmodule
yosys> help $reduce_xnor

A XNOR reduction. This corresponds to the Verilog unary prefix ‘~^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 156 simlib.v
385module \$reduce_xnor (A, Y);
386
387    parameter A_SIGNED = 0;
388    parameter A_WIDTH = 0;
389    parameter Y_WIDTH = 0;
390
391    input [A_WIDTH-1:0] A;
392    output [Y_WIDTH-1:0] Y;
393
394    generate
395        if (A_SIGNED) begin:BLOCK1
396            assign Y = ~^$signed(A);
397        end else begin:BLOCK2
398            assign Y = ~^A;
399        end
400    endgenerate
401
402endmodule
yosys> help $reduce_xor

A XOR reduction. This corresponds to the Verilog unary prefix ‘^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 157 simlib.v
357module \$reduce_xor (A, Y);
358
359    parameter A_SIGNED = 0;
360    parameter A_WIDTH = 0;
361    parameter Y_WIDTH = 0;
362
363    input [A_WIDTH-1:0] A;
364    output [Y_WIDTH-1:0] Y;
365
366    generate
367        if (A_SIGNED) begin:BLOCK1
368            assign Y = ^$signed(A);
369        end else begin:BLOCK2
370            assign Y = ^A;
371        end
372    endgenerate
373
374endmodule