Binary operators

All binary RTL cells have two input ports A and B and one output port Y. They also have the following parameters:

A_SIGNED

Set to a non-zero value if the input A is signed and therefore should be sign-extended when needed.

A_WIDTH

The width of the input port A.

B_SIGNED

Set to a non-zero value if the input B is signed and therefore should be sign-extended when needed.

B_WIDTH

The width of the input port B.

Y_WIDTH

The width of the output port Y.

Table 5 Cell types for binary operators with their corresponding Verilog expressions.

Verilog

Cell Type

Verilog

Cell Type

Y = A & B

$and

Y = A ** B

$pow

Y = A | B

$or

Y = A < B

$lt

Y = A ^ B

$xor

Y = A <= B

$le

Y = A ~^ B

$xnor

Y = A == B

$eq

Y = A << B

$shl

Y = A != B

$ne

Y = A >> B

$shr

Y = A >= B

$ge

Y = A <<< B

$sshl

Y = A > B

$gt

Y = A >>> B

$sshr

Y = A + B

$add

Y = A && B

$logic_and

Y = A - B

$sub

Y = A || B

$logic_or

Y = A * B

$mul

Y = A === B

$eqx

Y = A / B

$div

Y = A !== B

$nex

Y = A % B

$mod

N/A

$shift

N/A

$divfloor

N/A

$shiftx

N/A

$modfloor

The $shl and $shr cells implement logical shifts, whereas the $sshl and $sshr cells implement arithmetic shifts. The $shl and $sshl cells implement the same operation. All four of these cells interpret the second operand as unsigned, and require B_SIGNED to be zero.

Two additional shift operator cells are available that do not directly correspond to any operator in Verilog, $shift and $shiftx. The $shift cell performs a right logical shift if the second operand is positive (or unsigned), and a left logical shift if it is negative. The $shiftx cell performs the same operation as the $shift cell, but the vacated bit positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.

For the binary cells that output a logical value ($logic_and, $logic_or, $eqx, $nex, $lt, $le, $eq, $ne, $ge, $gt), when the Y_WIDTH parameter is greater than 1, the output is zero-extended, and only the least significant bit varies.

Division and modulo cells are available in two rounding modes. The original $div and $mod cells are based on truncating division, and correspond to the semantics of the verilog / and % operators. The $divfloor and $modfloor cells represent flooring division and flooring modulo, the latter of which corresponds to the % operator in Python. See the following table for a side-by-side comparison between the different semantics.

Table 6 Comparison between different rounding modes for division and modulo cells.

Division

Result

Truncating

Flooring

$div

$mod

$divfloor

$modfloor

-10 / 3

-3.3

-3

-1

-4

2

10 / -3

-3.3

-3

1

-4

-2

-10 / -3

3.3

3

-1

3

-1

10 / 3

3.3

3

1

3

1
yosys> help $add

Addition of inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘+’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 156 simlib.v
 981module \$add (A, B, Y);
 982
 983    parameter A_SIGNED = 0;
 984    parameter B_SIGNED = 0;
 985    parameter A_WIDTH = 0;
 986    parameter B_WIDTH = 0;
 987    parameter Y_WIDTH = 0;
 988
 989    input [A_WIDTH-1:0] A;
 990    input [B_WIDTH-1:0] B;
 991    output [Y_WIDTH-1:0] Y;
 992
 993    generate
 994        if (A_SIGNED && B_SIGNED) begin:BLOCK1
 995            assign Y = $signed(A) + $signed(B);
 996        end else begin:BLOCK2
 997            assign Y = A + B;
 998        end
 999    endgenerate
1000
1001endmodule
yosys> help $and

A bit-wise AND. This corresponds to the Verilog ‘&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 157 simlib.v
154module \$and (A, B, Y);
155
156    parameter A_SIGNED = 0;
157    parameter B_SIGNED = 0;
158    parameter A_WIDTH = 0;
159    parameter B_WIDTH = 0;
160    parameter Y_WIDTH = 0;
161
162    input [A_WIDTH-1:0] A;
163    input [B_WIDTH-1:0] B;
164    output [Y_WIDTH-1:0] Y;
165
166    generate
167        if (A_SIGNED && B_SIGNED) begin:BLOCK1
168            assign Y = $signed(A) & $signed(B);
169        end else begin:BLOCK2
170            assign Y = A & B;
171        end
172    endgenerate
173
174endmodule
yosys> help $bweqx

Bit-wise case equality

A bit-wise version of $eqx.

Properties:
Simulation model (verilog)
Listing 158 simlib.v
2013module \$bweqx (A, B, Y);
2014
2015    parameter WIDTH = 0;
2016
2017    input [WIDTH-1:0] A, B;
2018    output [WIDTH-1:0] Y;
2019
2020    genvar i;
2021    generate
2022        for (i = 0; i < WIDTH; i = i + 1) begin:slices
2023            assign Y[i] = A[i] === B[i];
2024        end
2025    endgenerate
2026
2027endmodule
yosys> help $div

Divider

This corresponds to the Verilog ‘/’ operator, performing division and truncating the result (rounding towards 0).

Properties:
Simulation model (verilog)
Listing 159 simlib.v
1340module \$div (A, B, Y);
1341
1342    parameter A_SIGNED = 0;
1343    parameter B_SIGNED = 0;
1344    parameter A_WIDTH = 0;
1345    parameter B_WIDTH = 0;
1346    parameter Y_WIDTH = 0;
1347
1348    input [A_WIDTH-1:0] A;
1349    input [B_WIDTH-1:0] B;
1350    output [Y_WIDTH-1:0] Y;
1351
1352    generate
1353        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1354            assign Y = $signed(A) / $signed(B);
1355        end else begin:BLOCK2
1356            assign Y = A / B;
1357        end
1358    endgenerate
1359
1360endmodule
yosys> help $divfloor

Division with floored result (rounded towards negative infinity).

Properties:

is_evaluable

Simulation model (verilog)
Listing 160 simlib.v
1403module \$divfloor (A, B, Y);
1404
1405    parameter A_SIGNED = 0;
1406    parameter B_SIGNED = 0;
1407    parameter A_WIDTH = 0;
1408    parameter B_WIDTH = 0;
1409    parameter Y_WIDTH = 0;
1410
1411    input [A_WIDTH-1:0] A;
1412    input [B_WIDTH-1:0] B;
1413    output [Y_WIDTH-1:0] Y;
1414
1415    generate
1416        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1417            localparam WIDTH =
1418                    A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
1419                    B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
1420            wire [WIDTH:0] A_buf, B_buf, N_buf;
1421            assign A_buf = $signed(A);
1422            assign B_buf = $signed(B);
1423            assign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));
1424            assign Y = $signed(N_buf) / $signed(B_buf);
1425        end else begin:BLOCK2
1426            assign Y = A / B;
1427        end
1428    endgenerate
1429
1430endmodule
yosys> help $eq

An equality comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘==’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 161 simlib.v
790module \$eq (A, B, Y);
791
792    parameter A_SIGNED = 0;
793    parameter B_SIGNED = 0;
794    parameter A_WIDTH = 0;
795    parameter B_WIDTH = 0;
796    parameter Y_WIDTH = 0;
797
798    input [A_WIDTH-1:0] A;
799    input [B_WIDTH-1:0] B;
800    output [Y_WIDTH-1:0] Y;
801
802    generate
803        if (A_SIGNED && B_SIGNED) begin:BLOCK1
804            assign Y = $signed(A) == $signed(B);
805        end else begin:BLOCK2
806            assign Y = A == B;
807        end
808    endgenerate
809
810endmodule
yosys> help $eqx

Case equality

An exact equality comparison between inputs ‘A’ and ‘B’. Also known as the case equality operator. This corresponds to the Verilog ‘===’ operator. Unlike equality comparison that can give ‘x’ as output, an exact equality comparison will strictly give ‘0’ or ‘1’ as output, even if input includes ‘x’ or ‘z’ values.

Properties:
Simulation model (verilog)
Listing 162 simlib.v
855module \$eqx (A, B, Y);
856
857    parameter A_SIGNED = 0;
858    parameter B_SIGNED = 0;
859    parameter A_WIDTH = 0;
860    parameter B_WIDTH = 0;
861    parameter Y_WIDTH = 0;
862
863    input [A_WIDTH-1:0] A;
864    input [B_WIDTH-1:0] B;
865    output [Y_WIDTH-1:0] Y;
866
867    generate
868        if (A_SIGNED && B_SIGNED) begin:BLOCK1
869            assign Y = $signed(A) === $signed(B);
870        end else begin:BLOCK2
871            assign Y = A === B;
872        end
873    endgenerate
874
875endmodule
yosys> help $ge

A greater-than-or-equal-to comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘>=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 163 simlib.v
918module \$ge (A, B, Y);
919
920    parameter A_SIGNED = 0;
921    parameter B_SIGNED = 0;
922    parameter A_WIDTH = 0;
923    parameter B_WIDTH = 0;
924    parameter Y_WIDTH = 0;
925
926    input [A_WIDTH-1:0] A;
927    input [B_WIDTH-1:0] B;
928    output [Y_WIDTH-1:0] Y;
929
930    generate
931        if (A_SIGNED && B_SIGNED) begin:BLOCK1
932            assign Y = $signed(A) >= $signed(B);
933        end else begin:BLOCK2
934            assign Y = A >= B;
935        end
936    endgenerate
937
938endmodule
yosys> help $gt

A greater-than comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 164 simlib.v
950module \$gt (A, B, Y);
951
952    parameter A_SIGNED = 0;
953    parameter B_SIGNED = 0;
954    parameter A_WIDTH = 0;
955    parameter B_WIDTH = 0;
956    parameter Y_WIDTH = 0;
957
958    input [A_WIDTH-1:0] A;
959    input [B_WIDTH-1:0] B;
960    output [Y_WIDTH-1:0] Y;
961
962    generate
963        if (A_SIGNED && B_SIGNED) begin:BLOCK1
964            assign Y = $signed(A) > $signed(B);
965        end else begin:BLOCK2
966            assign Y = A > B;
967        end
968    endgenerate
969
970endmodule
yosys> help $le

A less-than-or-equal-to comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘<=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 165 simlib.v
758module \$le (A, B, Y);
759
760    parameter A_SIGNED = 0;
761    parameter B_SIGNED = 0;
762    parameter A_WIDTH = 0;
763    parameter B_WIDTH = 0;
764    parameter Y_WIDTH = 0;
765
766    input [A_WIDTH-1:0] A;
767    input [B_WIDTH-1:0] B;
768    output [Y_WIDTH-1:0] Y;
769
770    generate
771        if (A_SIGNED && B_SIGNED) begin:BLOCK1
772            assign Y = $signed(A) <= $signed(B);
773        end else begin:BLOCK2
774            assign Y = A <= B;
775        end
776    endgenerate
777
778endmodule
yosys> help $logic_and

A logical AND. This corresponds to the Verilog ‘&&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 166 simlib.v
1549module \$logic_and (A, B, Y);
1550
1551    parameter A_SIGNED = 0;
1552    parameter B_SIGNED = 0;
1553    parameter A_WIDTH = 0;
1554    parameter B_WIDTH = 0;
1555    parameter Y_WIDTH = 0;
1556
1557    input [A_WIDTH-1:0] A;
1558    input [B_WIDTH-1:0] B;
1559    output [Y_WIDTH-1:0] Y;
1560
1561    generate
1562        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1563            assign Y = $signed(A) && $signed(B);
1564        end else begin:BLOCK2
1565            assign Y = A && B;
1566        end
1567    endgenerate
1568
1569endmodule
yosys> help $logic_or

A logical OR. This corresponds to the Verilog ‘||’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 167 simlib.v
1580module \$logic_or (A, B, Y);
1581
1582    parameter A_SIGNED = 0;
1583    parameter B_SIGNED = 0;
1584    parameter A_WIDTH = 0;
1585    parameter B_WIDTH = 0;
1586    parameter Y_WIDTH = 0;
1587
1588    input [A_WIDTH-1:0] A;
1589    input [B_WIDTH-1:0] B;
1590    output [Y_WIDTH-1:0] Y;
1591
1592    generate
1593        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1594            assign Y = $signed(A) || $signed(B);
1595        end else begin:BLOCK2
1596            assign Y = A || B;
1597        end
1598    endgenerate
1599
1600endmodule
yosys> help $lt

A less-than comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 168 simlib.v
726module \$lt (A, B, Y);
727
728    parameter A_SIGNED = 0;
729    parameter B_SIGNED = 0;
730    parameter A_WIDTH = 0;
731    parameter B_WIDTH = 0;
732    parameter Y_WIDTH = 0;
733
734    input [A_WIDTH-1:0] A;
735    input [B_WIDTH-1:0] B;
736    output [Y_WIDTH-1:0] Y;
737
738    generate
739        if (A_SIGNED && B_SIGNED) begin:BLOCK1
740            assign Y = $signed(A) < $signed(B);
741        end else begin:BLOCK2
742            assign Y = A < B;
743        end
744    endgenerate
745
746endmodule
yosys> help $mod

Modulo

This corresponds to the Verilog ‘%’ operator, giving the module (or remainder) of division and truncating the result (rounding towards 0).

Invariant: $div(A, B) * B + $mod(A, B) == A

Properties:
Simulation model (verilog)
Listing 169 simlib.v
1372module \$mod (A, B, Y);
1373
1374    parameter A_SIGNED = 0;
1375    parameter B_SIGNED = 0;
1376    parameter A_WIDTH = 0;
1377    parameter B_WIDTH = 0;
1378    parameter Y_WIDTH = 0;
1379
1380    input [A_WIDTH-1:0] A;
1381    input [B_WIDTH-1:0] B;
1382    output [Y_WIDTH-1:0] Y;
1383
1384    generate
1385        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1386            assign Y = $signed(A) % $signed(B);
1387        end else begin:BLOCK2
1388            assign Y = A % B;
1389        end
1390    endgenerate
1391
1392endmodule
yosys> help $modfloor

Modulo/remainder of division with floored result (rounded towards negative infinity).

Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A

Properties:

is_evaluable

Simulation model (verilog)
Listing 170 simlib.v
1443module \$modfloor (A, B, Y);
1444
1445    parameter A_SIGNED = 0;
1446    parameter B_SIGNED = 0;
1447    parameter A_WIDTH = 0;
1448    parameter B_WIDTH = 0;
1449    parameter Y_WIDTH = 0;
1450
1451    input [A_WIDTH-1:0] A;
1452    input [B_WIDTH-1:0] B;
1453    output [Y_WIDTH-1:0] Y;
1454
1455    generate
1456        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1457            localparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
1458            wire [WIDTH-1:0] B_buf, Y_trunc;
1459            assign B_buf = $signed(B);
1460            assign Y_trunc = $signed(A) % $signed(B);
1461            // flooring mod is the same as truncating mod for positive division results (A and B have
1462            // the same sign), as well as when there's no remainder.
1463            // For all other cases, they behave as `floor - trunc = B`
1464            assign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);
1465        end else begin:BLOCK2
1466            // no difference between truncating and flooring for unsigned
1467            assign Y = A % B;
1468        end
1469    endgenerate
1470
1471endmodule
yosys> help $mul

Multiplication of inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘*’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 171 simlib.v
1045module \$mul (A, B, Y);
1046
1047    parameter A_SIGNED = 0;
1048    parameter B_SIGNED = 0;
1049    parameter A_WIDTH = 0;
1050    parameter B_WIDTH = 0;
1051    parameter Y_WIDTH = 0;
1052
1053    input [A_WIDTH-1:0] A;
1054    input [B_WIDTH-1:0] B;
1055    output [Y_WIDTH-1:0] Y;
1056
1057    generate
1058        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1059            assign Y = $signed(A) * $signed(B);
1060        end else begin:BLOCK2
1061            assign Y = A * B;
1062        end
1063    endgenerate
1064
1065endmodule
yosys> help $ne

An inequality comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘!=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 172 simlib.v
822module \$ne (A, B, Y);
823
824    parameter A_SIGNED = 0;
825    parameter B_SIGNED = 0;
826    parameter A_WIDTH = 0;
827    parameter B_WIDTH = 0;
828    parameter Y_WIDTH = 0;
829
830    input [A_WIDTH-1:0] A;
831    input [B_WIDTH-1:0] B;
832    output [Y_WIDTH-1:0] Y;
833
834    generate
835        if (A_SIGNED && B_SIGNED) begin:BLOCK1
836            assign Y = $signed(A) != $signed(B);
837        end else begin:BLOCK2
838            assign Y = A != B;
839        end
840    endgenerate
841
842endmodule
yosys> help $nex

Case inequality

This corresponds to the Verilog ‘!==’ operator.

Refer to $eqx for more details.

Properties:
Simulation model (verilog)
Listing 173 simlib.v
886module \$nex (A, B, Y);
887
888    parameter A_SIGNED = 0;
889    parameter B_SIGNED = 0;
890    parameter A_WIDTH = 0;
891    parameter B_WIDTH = 0;
892    parameter Y_WIDTH = 0;
893
894    input [A_WIDTH-1:0] A;
895    input [B_WIDTH-1:0] B;
896    output [Y_WIDTH-1:0] Y;
897
898    generate
899        if (A_SIGNED && B_SIGNED) begin:BLOCK1
900            assign Y = $signed(A) !== $signed(B);
901        end else begin:BLOCK2
902            assign Y = A !== B;
903        end
904    endgenerate
905
906endmodule
yosys> help $or

A bit-wise OR. This corresponds to the Verilog ‘|’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 174 simlib.v
185module \$or (A, B, Y);
186
187    parameter A_SIGNED = 0;
188    parameter B_SIGNED = 0;
189    parameter A_WIDTH = 0;
190    parameter B_WIDTH = 0;
191    parameter Y_WIDTH = 0;
192
193    input [A_WIDTH-1:0] A;
194    input [B_WIDTH-1:0] B;
195    output [Y_WIDTH-1:0] Y;
196
197    generate
198        if (A_SIGNED && B_SIGNED) begin:BLOCK1
199            assign Y = $signed(A) | $signed(B);
200        end else begin:BLOCK2
201            assign Y = A | B;
202        end
203    endgenerate
204
205endmodule
yosys> help $pow

Exponentiation of an input (Y = A ** B). This corresponds to the Verilog ‘**’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 175 simlib.v
1485module \$pow (A, B, Y);
1486
1487    parameter A_SIGNED = 0;
1488    parameter B_SIGNED = 0;
1489    parameter A_WIDTH = 0;
1490    parameter B_WIDTH = 0;
1491    parameter Y_WIDTH = 0;
1492
1493    input [A_WIDTH-1:0] A;
1494    input [B_WIDTH-1:0] B;
1495    output [Y_WIDTH-1:0] Y;
1496
1497    generate
1498        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1499            assign Y = $signed(A) ** $signed(B);
1500        end else if (A_SIGNED) begin:BLOCK2
1501            assign Y = $signed(A) ** B;
1502        end else if (B_SIGNED) begin:BLOCK3
1503            assign Y = A ** $signed(B);
1504        end else begin:BLOCK4
1505            assign Y = A ** B;
1506        end
1507    endgenerate
1508
1509endmodule
yosys> help $shift

Variable shifter

Performs a right logical shift if the second operand is positive (or unsigned), and a left logical shift if it is negative.

Properties:

is_evaluable

Simulation model (verilog)
Listing 176 simlib.v
543module \$shift (A, B, Y);
544
545    parameter A_SIGNED = 0;
546    parameter B_SIGNED = 0;
547    parameter A_WIDTH = 0;
548    parameter B_WIDTH = 0;
549    parameter Y_WIDTH = 0;
550
551    input [A_WIDTH-1:0] A;
552    input [B_WIDTH-1:0] B;
553    output [Y_WIDTH-1:0] Y;
554
555    generate
556        if (A_SIGNED) begin:BLOCK1
557            if (B_SIGNED) begin:BLOCK2
558                assign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;
559            end else begin:BLOCK3
560                assign Y = $signed(A) >> B;
561            end
562        end else begin:BLOCK4
563            if (B_SIGNED) begin:BLOCK5
564                assign Y = $signed(B) < 0 ? A << -B : A >> B;
565            end else begin:BLOCK6
566                assign Y = A >> B;
567            end
568        end
569    endgenerate
570
571endmodule
yosys> help $shiftx

Indexed part-select

Same as the $shift cell, but fills with ‘x’.

Properties:
Simulation model (verilog)
Listing 177 simlib.v
580module \$shiftx (A, B, Y);
581
582    parameter A_SIGNED = 0;
583    parameter B_SIGNED = 0;
584    parameter A_WIDTH = 0;
585    parameter B_WIDTH = 0;
586    parameter Y_WIDTH = 0;
587
588    input [A_WIDTH-1:0] A;
589    input [B_WIDTH-1:0] B;
590    output [Y_WIDTH-1:0] Y;
591
592    generate
593        if (Y_WIDTH > 0)
594            if (B_SIGNED) begin:BLOCK1
595                assign Y = A[$signed(B) +: Y_WIDTH];
596            end else begin:BLOCK2
597                assign Y = A[B +: Y_WIDTH];
598            end
599    endgenerate
600
601endmodule
yosys> help $shl

A logical shift-left operation. This corresponds to the Verilog ‘<<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 178 simlib.v
419module \$shl (A, B, Y);
420
421    parameter A_SIGNED = 0;
422    parameter B_SIGNED = 0;
423    parameter A_WIDTH = 0;
424    parameter B_WIDTH = 0;
425    parameter Y_WIDTH = 0;
426
427    input [A_WIDTH-1:0] A;
428    input [B_WIDTH-1:0] B;
429    output [Y_WIDTH-1:0] Y;
430
431    generate
432        if (A_SIGNED) begin:BLOCK1
433            assign Y = $signed(A) << B;
434        end else begin:BLOCK2
435            assign Y = A << B;
436        end
437    endgenerate
438
439endmodule
yosys> help $shr

A logical shift-right operation. This corresponds to the Verilog ‘>>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 179 simlib.v
450module \$shr (A, B, Y);
451
452    parameter A_SIGNED = 0;
453    parameter B_SIGNED = 0;
454    parameter A_WIDTH = 0;
455    parameter B_WIDTH = 0;
456    parameter Y_WIDTH = 0;
457
458    input [A_WIDTH-1:0] A;
459    input [B_WIDTH-1:0] B;
460    output [Y_WIDTH-1:0] Y;
461
462    generate
463        if (A_SIGNED) begin:BLOCK1
464            assign Y = $signed(A) >> B;
465        end else begin:BLOCK2
466            assign Y = A >> B;
467        end
468    endgenerate
469
470endmodule
yosys> help $sshl

An arithmatic shift-left operation. This corresponds to the Verilog ‘<<<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 180 simlib.v
482module \$sshl (A, B, Y);
483
484    parameter A_SIGNED = 0;
485    parameter B_SIGNED = 0;
486    parameter A_WIDTH = 0;
487    parameter B_WIDTH = 0;
488    parameter Y_WIDTH = 0;
489
490    input [A_WIDTH-1:0] A;
491    input [B_WIDTH-1:0] B;
492    output [Y_WIDTH-1:0] Y;
493
494    generate
495        if (A_SIGNED) begin:BLOCK1
496            assign Y = $signed(A) <<< B;
497        end else begin:BLOCK2
498            assign Y = A <<< B;
499        end
500    endgenerate
501
502endmodule
yosys> help $sshr

An arithmatic shift-right operation. This corresponds to the Verilog ‘>>>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 181 simlib.v
514module \$sshr (A, B, Y);
515
516    parameter A_SIGNED = 0;
517    parameter B_SIGNED = 0;
518    parameter A_WIDTH = 0;
519    parameter B_WIDTH = 0;
520    parameter Y_WIDTH = 0;
521
522    input [A_WIDTH-1:0] A;
523    input [B_WIDTH-1:0] B;
524    output [Y_WIDTH-1:0] Y;
525
526    generate
527        if (A_SIGNED) begin:BLOCK1
528            assign Y = $signed(A) >>> B;
529        end else begin:BLOCK2
530            assign Y = A >>> B;
531        end
532    endgenerate
533
534endmodule
yosys> help $sub

Subtraction between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘-’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 182 simlib.v
1013module \$sub (A, B, Y);
1014
1015    parameter A_SIGNED = 0;
1016    parameter B_SIGNED = 0;
1017    parameter A_WIDTH = 0;
1018    parameter B_WIDTH = 0;
1019    parameter Y_WIDTH = 0;
1020
1021    input [A_WIDTH-1:0] A;
1022    input [B_WIDTH-1:0] B;
1023    output [Y_WIDTH-1:0] Y;
1024
1025    generate
1026        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1027            assign Y = $signed(A) - $signed(B);
1028        end else begin:BLOCK2
1029            assign Y = A - B;
1030        end
1031    endgenerate
1032
1033endmodule
yosys> help $xnor

A bit-wise XNOR. This corresponds to the Verilog ‘~^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 183 simlib.v
247module \$xnor (A, B, Y);
248
249    parameter A_SIGNED = 0;
250    parameter B_SIGNED = 0;
251    parameter A_WIDTH = 0;
252    parameter B_WIDTH = 0;
253    parameter Y_WIDTH = 0;
254
255    input [A_WIDTH-1:0] A;
256    input [B_WIDTH-1:0] B;
257    output [Y_WIDTH-1:0] Y;
258
259    generate
260        if (A_SIGNED && B_SIGNED) begin:BLOCK1
261            assign Y = $signed(A) ~^ $signed(B);
262        end else begin:BLOCK2
263            assign Y = A ~^ B;
264        end
265    endgenerate
266
267endmodule
yosys> help $xor

A bit-wise XOR. This corresponds to the Verilog ‘^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 184 simlib.v
216module \$xor (A, B, Y);
217
218    parameter A_SIGNED = 0;
219    parameter B_SIGNED = 0;
220    parameter A_WIDTH = 0;
221    parameter B_WIDTH = 0;
222    parameter Y_WIDTH = 0;
223
224    input [A_WIDTH-1:0] A;
225    input [B_WIDTH-1:0] B;
226    output [Y_WIDTH-1:0] Y;
227
228    generate
229        if (A_SIGNED && B_SIGNED) begin:BLOCK1
230            assign Y = $signed(A) ^ $signed(B);
231        end else begin:BLOCK2
232            assign Y = A ^ B;
233        end
234    endgenerate
235
236endmodule