Generic

prep - generic synthesis script

yosys> help prep
prep [options]
This command runs a conservative RTL synthesis. A typical application for this
is the preparation stage of a verification flow. This command does not operate
on partly selected designs.
-top <module>
use the specified module as top module (default='top')
-auto-top
automatically determine the top of the design hierarchy
-flatten
flatten the design before synthesis. this will pass '-auto-top' to
'hierarchy' if no top module is specified.
-ifx
passed to 'proc'. uses verilog simulation behavior for verilog if/case
undef handling. this also prevents 'wreduce' from being run.
-memx
simulate verilog simulation behavior for out-of-bounds memory accesses
using the 'memory_memx' pass.
-nomem
do not run any of the memory_* passes
-rdff
call 'memory_dff'. This enables merging of FFs into
memory read ports.
-nokeepdc
do not call opt_* with -keepdc
-run <from_label>[:<to_label>]
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.

The following commands are executed by this synthesis command:

begin:
    hierarchy -check [-top <top> | -auto-top]

coarse:
    proc [-ifx]
    flatten    (if -flatten)
    future
    opt_expr -keepdc
    opt_clean
    check
    opt -noff -keepdc
    wreduce -keepdc [-memx]
    memory_dff    (if -rdff)
    memory_memx    (if -memx)
    opt_clean
    memory_collect
    opt -noff -keepdc -fast

check:
    stat
    check

Note

Help text automatically generated from techlibs/common/prep.cc:30

synth - generic synthesis script

yosys> help synth
synth [options]
This command runs the default synthesis script. This command does not operate
on partly selected designs.
-top <module>
use the specified module as top module (default='top')
-auto-top
automatically determine the top of the design hierarchy
-flatten
flatten the design before synthesis. this will pass '-auto-top' to
'hierarchy' if no top module is specified.
-hieropt
enable hierarchical optimization. this option is useful when `-flatten'
is not used, or when selected modules are marked with 'keep_hierarchy'

.        to prevent their dissolution.
-encfile <file>
passed to 'fsm_recode' via 'fsm'
-lut <k>
perform synthesis for a k-LUT architecture.
-nofsm
do not run FSM optimization
-noabc
do not run abc (as if yosys was compiled without ABC support)
-booth
run the booth pass to map $mul to Booth encoded multipliers
-noalumacc
do not run 'alumacc' pass. i.e. keep arithmetic operators in
their direct form ($add, $sub, etc.).
-nordff
passed to 'memory'. prohibits merging of FFs into memory read ports
-noshare
do not run SAT-based resource sharing
-run <from_label>[:<to_label>]
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
-abc9
use new ABC9 flow (EXPERIMENTAL)
-flowmap
use FlowMap LUT techmapping instead of ABC
-no-rw-check
marks all recognized read ports as "return don't-care value on
read/write collision" (same result as setting the no_rw_check
attribute on all memories).
-extra-map filename
source extra rules from the given file to complement the default
mapping library in the `techmap` step. this option can be
repeated.
-relativeshare
use paths relative to share directory for source locations
where possible (experimental).

The following commands are executed by this synthesis command:

begin:
    hierarchy -check [-top <top> | -auto-top]

coarse:
    proc
    flatten      (if -flatten)
    opt_expr
    opt_clean
    check
    opt -nodffe -nosdff
    fsm          (unless -nofsm)
    opt [-hier]
    wreduce
    peepopt
    opt_clean
    techmap -map +/cmp2lut.v -map +/cmp2lcu.v     (if -lut)
    booth        (if -booth)
    alumacc      (unless -noalumacc)
    share        (unless -noshare)
    opt [-hier]
    memory -nomap
    opt_clean

fine:
    opt -fast -full [-hier]
    memory_map
    opt -full
    techmap                      (unless -extra-map)
    techmap -map +/techmap.v -map <inject>      (if -extra-map)
    techmap -map +/gate2lut.v    (if -noabc and -lut)
    clean; opt_lut               (if -noabc and -lut)
    flowmap -maxlut K            (if -flowmap and -lut)
    opt -fast [-hier]
    abc -fast           (unless -noabc, unless -lut)
    abc -fast -lut k    (unless -noabc, if -lut)
    opt -fast           (unless -noabc)

check:
    hierarchy -check
    stat
    check

Note

Help text automatically generated from techlibs/common/synth.cc:29