Command line reference

Usage:
  ./yosys [OPTION...] [<infile> [..]]

 operation options:
  -b, --backend <backend>       use <backend> for the output file specified on the command line
  -f, --frontend <frontend>     use <frontend> for the input files on the command line
  -s, --scriptfile <scriptfile>
                                execute the commands in <scriptfile>
  -c, --tcl-scriptfile <tcl_scriptfile>
                                execute the commands in the TCL <tcl_scriptfile> (see 'help tcl' for details)
  -C, --tcl-interactive         enters TCL interactive shell mode
  -p, --commands <commands>     execute <commands> (to chain commands, separate them with semicolon + whitespace: 'cmd1; cmd2')
  -r, --top <top>               elaborate the specified HDL <top> module
  -m, --plugin <plugin>         load the specified <plugin> module
  -D, --define <define>[=<value>]
                                set the specified Verilog define to <value> if supplied via command "read -define"
  -S, --synth                   shortcut for calling the "synth" command, a default script for transforming the Verilog input to a gate-level netlist. For example: yosys -o output.blif -S input.v For more complex synthesis jobs it is recommended to use the read_* and write_* commands in a script file instead of specifying input and output files on the command line.
  -H                            print the command list
  -h, --help [<command>]        print this help message. If given, print help for <command>.
  -V, --version                 print version information and exit

 logging options:
  -Q                            suppress printing of banner (copyright, disclaimer, version)
  -T                            suppress printing of footer (log hash, version, timing statistics)
      --no-version              suppress writing out Yosys version anywhere excluding -V, --version
  -q, --quiet                   quiet operation. Only write warnings and error messages to console. Use this option twice to also quiet warning messages
  -v, --verbose <level>         print log headers up to <level> to the console. Implies -q for everything except the 'End of script.' message.
  -t, --timestamp               annotate all log messages with a time stamp
  -d, --detailed-timing         print more detailed timing stats at exit
  -l, --logfile <logfile>       write log messages to <logfile>
  -L, --line-buffered-logfile <logfile>
                                like -l but open <logfile> in line buffered mode
  -o, --outfile <outfile>       write the design to <outfile> on exit
  -P, --dump-design <header_id>[:<filename>]
                                dump the design when printing the specified log header to a file. yosys_dump_<header_id>.il is used as filename if none is specified. Use 'ALL' as <header_id> to dump at every header.
  -W, --warning-as-warning <regex>
                                print a warning for all log messages matching <regex>
  -w, --warning-as-message <regex>
                                if a warning message matches <regex>, it is printed as regular message instead
  -e, --warning-as-error <regex>
                                if a warning message matches <regex>, it is printed as error message instead
  -E, --deps-file <depsfile>    write a Makefile dependencies file <depsfile> with input and output file names

 developer options:
  -X, --trace                   enable tracing of core data structure changes. for debugging
  -M, --randomize-pointers      will slightly randomize allocated pointer addresses. for debugging
      --autoidx <idx>           start counting autoidx up from <seed>, similar effect to --hash-seed
      --hash-seed <seed>        mix up hashing values with <seed>, for extreme optimization and testing
  -A, --abort                   will call abort() at the end of the script. for debugging
  -x, --experimental <feature>  do not print warnings for the experimental <feature>
  -g, --debug                   globally enable debug log messages
      --perffile <perffile>     write a JSON performance log to <perffile>

Command reference

List of all commands

• Yosys environment variables
• Reading input files
  • connect_rpc - connect to RPC frontend
  • read - load HDL designs
  • read_aiger - read AIGER file
  • read_blif - read BLIF file
  • read_json - read JSON file
  • read_liberty - read cells from liberty file
  • read_rtlil - read modules from RTLIL file
  • read_verilog - read modules from Verilog file
  • read_verilog_file_list - parse a Verilog file list
  • read_xaiger2 - (experimental) read XAIGER file
  • verific - load Verilog and VHDL designs using Verific
  • verilog_defaults - set default options for read_verilog
  • verilog_defines - define and undefine verilog defines
• Writing output files
  • dump - print parts of the design in RTLIL format
  • jny - write design and metadata
  • json - write design in JSON format
  • write_aiger - write design to AIGER file
  • write_aiger2 - (experimental) write design to AIGER file
  • write_blif - write design to BLIF file
  • write_btor - write design to BTOR file
  • write_cxxrtl - convert design to C++ RTL simulation
  • write_edif - write design to EDIF netlist file
  • write_firrtl - write design to a FIRRTL file
  • write_functional_cxx - convert design to C++ using the functional backend
  • write_functional_rosette - Generate Rosette compatible Racket from Functional IR
  • write_functional_smt2 - Generate SMT-LIB from Functional IR
  • write_intersynth - write design to InterSynth netlist file
  • write_jny - generate design metadata
  • write_json - write design to a JSON file
  • write_rtlil - write design to RTLIL file
  • write_simplec - convert design to simple C code
  • write_smt2 - write design to SMT-LIBv2 file
  • write_smv - write design to SMV file
  • write_spice - write design to SPICE netlist file
  • write_table - write design as connectivity table
  • write_verilog - write design to Verilog file
  • write_xaiger - write design to XAIGER file
  • write_xaiger2 - (experimental) write module to XAIGER file
• Yosys kernel commands
  • echo - turning echoing back of commands on and off
  • help - display help messages
  • history - show last interactive commands
  • license - print license terms
  • script - execute commands from file or wire
  • shell - enter interactive command mode
  • tcl - execute a TCL script file
• Formal verification
  • assertpmux - adds asserts for parallel muxes
  • async2sync - convert async FF inputs to sync circuits
  • chformal - change formal constraints of the design
  • clk2fflogic - convert clocked FFs to generic $ff cells
  • cutpoint - adds formal cut points to the design
  • dft_tag - create tagging logic for data flow tracking
  • fmcombine - combine two instances of a cell into one
  • fminit - set init values/sequences for formal
  • formalff - prepare FFs for formal
  • freduce - perform functional reduction
  • future - resolve future sampled value functions
  • glift - create GLIFT models and optimization problems
  • miter - automatically create a miter circuit
  • mutate - generate or apply design mutations
  • qbfsat - solve a 2QBF-SAT problem in the circuit
  • sat - solve a SAT problem in the circuit
  • supercover - add hi/lo cover cells for each wire bit
  • synthprop - synthesize SVA properties
  • xprop - formal x propagation

• Passes
  • Working with hierarchy
    • flatten - flatten design
    • hierarchy - check, expand and clean up design hierarchy
    • keep_hierarchy - selectively add the keep_hierarchy attribute
    • submod - moving part of a module to a new submodule
    • uniquify - create unique copies of modules
  • Converting process blocks
    • proc - translate processes to netlists
    • proc_arst - detect asynchronous resets
    • proc_clean - remove empty parts of processes
    • proc_dff - extract flip-flops from processes
    • proc_dlatch - extract latches from processes
    • proc_init - convert initial block to init attributes
    • proc_memwr - extract memory writes from processes
    • proc_mux - convert decision trees to multiplexers
    • proc_prune - remove redundant assignments
    • proc_rmdead - eliminate dead trees in decision trees
    • proc_rom - convert switches to ROMs
  • FSM handling
    • fsm - extract and optimize finite state machines
    • fsm_detect - finding FSMs in design
    • fsm_expand - expand FSM cells by merging logic into it
    • fsm_export - exporting FSMs to KISS2 files
    • fsm_extract - extracting FSMs in design
    • fsm_info - print information on finite state machines
    • fsm_map - mapping FSMs to basic logic
    • fsm_opt - optimize finite state machines
    • fsm_recode - recoding finite state machines
  • Memory handling
    • memory - translate memories to basic cells
    • memory_bmux2rom - convert muxes to ROMs
    • memory_bram - map memories to block rams
    • memory_collect - creating multi-port memory cells
    • memory_dff - merge input/output DFFs into memory read ports
    • memory_libmap - map memories to cells
    • memory_map - translate multiport memories to basic cells
    • memory_memx - emulate vlog sim behavior for mem ports
    • memory_narrow - split up wide memory ports
    • memory_nordff - extract read port FFs from memories
    • memory_share - consolidate memory ports
    • memory_unpack - unpack multi-port memory cells
  • Optimization passes
    • clean - remove unused cells and wires
    • muxpack - $mux/$pmux cascades to $pmux
    • onehot - optimize $eq cells for onehot signals
    • opt - perform simple optimizations
    • opt_clean - remove unused cells and wires
    • opt_demorgan - Optimize reductions with DeMorgan equivalents
    • opt_dff - perform DFF optimizations
    • opt_expr - perform const folding and simple expression rewriting
    • opt_ffinv - push inverters through FFs
    • opt_hier - perform cross-boundary optimization
    • opt_lut - optimize LUT cells
    • opt_lut_ins - discard unused LUT inputs
    • opt_mem - optimize memories
    • opt_mem_feedback - convert memory read-to-write port feedback paths to write enables
    • opt_mem_priority - remove priority relations between write ports that can never collide
    • opt_mem_widen - optimize memories where all ports are wide
    • opt_merge - consolidate identical cells
    • opt_muxtree - eliminate dead trees in multiplexer trees
    • opt_reduce - simplify large MUXes and AND/OR gates
    • opt_share - merge mutually exclusive cells of the same type that share an input signal
    • peepopt - collection of peephole optimizers
    • pmux2shiftx - transform $pmux cells to $shiftx cells
    • recover_names - Execute a lossy mapping command and recover original netnames
    • share - perform sat-based resource sharing
    • wreduce - reduce the word size of operations if possible
  • Technology mapping
    • abc - use ABC for technology mapping
    • abc9 - use ABC9 for technology mapping
    • abc9_exe - use ABC9 for technology mapping
    • abc9_ops - helper functions for ABC9
    • abc_new - (experimental) use ABC for SC technology mapping (new)
    • aigmap - map logic to and-inverter-graph circuit
    • alumacc - extract ALU and MACC cells
    • attrmap - renaming attributes
    • attrmvcp - move or copy attributes from wires to driving cells
    • bmuxmap - transform $bmux cells to trees of $mux cells
    • booth - map $mul cells to Booth multipliers
    • bufnorm - (experimental) convert design into buffered-normalized form
    • bwmuxmap - replace $bwmux cells with equivalent logic
    • cellmatch - match cells to their targets in cell library
    • clkbufmap - insert clock buffers on clock networks
    • clockgate - extract clock gating out of flip flops
    • constmap - technology mapping of coarse constant value
    • deminout - demote inout ports to input or output
    • demuxmap - transform $demux cells to $eq + $mux cells
    • dffinit - set INIT param on FF cells
    • dfflegalize - convert FFs to types supported by the target
    • dfflibmap - technology mapping of flip-flops
    • dffunmap - unmap clock enable and synchronous reset from FFs
    • extract - find subcircuits and replace them with cells
    • extract_counter - Extract GreenPak4 counter cells
    • extract_fa - find and extract full/half adders
    • extract_reduce - converts gate chains into $reduce_* cells
    • extractinv - extract explicit inverter cells for invertible cell pins
    • flowmap - pack LUTs with FlowMap
    • hilomap - technology mapping of constant hi- and/or lo-drivers
    • insbuf - insert buffer cells for connected wires
    • iopadmap - technology mapping of i/o pads (or buffers)
    • libcache - control caching of technology library data parsed from liberty files
    • lut2mux - convert $lut to $_MUX_
    • maccmap - mapping macc cells
    • muxcover - cover trees of MUX cells with wider MUXes
    • nlutmap - map to LUTs of different sizes
    • paramap - renaming cell parameters
    • pmuxtree - transform $pmux cells to trees of $mux cells
    • shregmap - map shift registers
    • simplemap - mapping simple coarse-grain cells
    • techmap - generic technology mapper
    • tribuf - infer tri-state buffers
    • zinit - add inverters so all FF are zero-initialized
  • Design modification
    • abstract - replace signals with abstract values during formal verification
    • add - add objects to the design
    • autoname - automatically assign names to objects
    • blackbox - convert modules into blackbox modules
    • box_derive - derive box modules
    • bugpoint - minimize testcases
    • chparam - re-evaluate modules with new parameters
    • chtype - change type of cells in the design
    • clean_zerowidth - clean zero-width connections from the design
    • connect - create or remove connections
    • connwrappers - match width of input-output port pairs
    • copy - copy modules in the design
    • delete - delete objects in the design
    • design - save, restore and reset current design
    • expose - convert internal signals to module ports
    • linecoverage - report coverage information
    • rename - rename object in the design
    • scatter - add additional intermediate nets
    • setattr - set/unset attributes on objects
    • setparam - set/unset parameters on objects
    • setundef - replace undef values with defined constants
    • sort - sort the design objects
    • splice - create explicit splicing cells
    • splitcells - split up multi-bit cells
    • splitnets - split up multi-bit nets
    • test_select - call internal selection methods on design for testing purposes
    • timeest - estimate timing
    • wbflip - flip the whitebox attribute
    • wrapcell - wrap individual cells into new modules
  • Equivalence checking
    • equiv_add - add a $equiv cell
    • equiv_induct - proving $equiv cells using temporal induction
    • equiv_make - prepare a circuit for equivalence checking
    • equiv_mark - mark equivalence checking regions
    • equiv_miter - extract miter from equiv circuit
    • equiv_opt - prove equivalence for optimized circuit
    • equiv_purge - purge equivalence checking module
    • equiv_remove - remove $equiv cells
    • equiv_simple - try proving simple $equiv instances
    • equiv_status - print status of equivalent checking module
    • equiv_struct - structural equivalence checking
  • Simulating circuits
    • eval - evaluate the circuit given an input
    • fst2tb - generate testbench out of fst file
    • sim - simulate the circuit
  • Design status
    • cd - a shortcut for ‘select -module <name>’
    • check - check for obvious problems in the design
    • cover - print code coverage counters
    • debug - run command with debug log messages enabled
    • edgetypes - list all types of edges in selection
    • exec - execute commands in the operating system shell
    • log - print text and log files
    • logger - set logger properties
    • ls - list modules or objects in modules
    • ltp - print longest topological path
    • plugin - load and list loaded plugins
    • portarcs - derive port arcs for propagation delay
    • portlist - list (top-level) ports
    • printattrs - print attributes of selected objects
    • scc - detect strongly connected components (logic loops)
    • scratchpad - get/set values in the scratchpad
    • select - modify and view the list of selected objects
    • setenv - set an environment variable
    • show - generate schematics using graphviz
    • sta - perform static timing analysis
    • stat - print some statistics
    • tee - redirect command output to file
    • torder - print cells in topological order
    • trace - redirect command output to file
    • viz - visualize data flow graph
    • write_file - write a text to a file
• Technology libraries
  • Generic
    • prep - generic synthesis script
    • synth - generic synthesis script
  • Achronix
    • synth_achronix - synthesis for Achronix Speedster22i FPGAs.
  • Anlogic
    • anlogic_eqn - Anlogic: Calculate equations for luts
    • anlogic_fixcarry - Anlogic: fix carry chain
    • synth_anlogic - synthesis for Anlogic FPGAs
  • CoolRunner-II
    • coolrunner2_fixup - insert necessary buffer cells for CoolRunner-II architecture
    • coolrunner2_sop - break $sop cells into ANDTERM/ORTERM cells
    • synth_coolrunner2 - synthesis for Xilinx Coolrunner-II CPLDs
  • eASIC
    • synth_easic - synthesis for eASIC platform
  • FABulous
    • synth_fabulous - FABulous synthesis script
  • Gatemate
    • gatemate_foldinv - fold inverters into Gatemate LUT trees
    • synth_gatemate - synthesis for Cologne Chip GateMate FPGAs
  • Gowin
    • synth_gowin - synthesis for Gowin FPGAs
  • GreenPAK4
    • greenpak4_dffinv - merge greenpak4 inverters and DFF/latches
    • rmports - remove module ports with no connections
    • synth_greenpak4 - synthesis for GreenPAK4 FPGAs
  • iCE40
    • ice40_braminit - iCE40: perform SB_RAM40_4K initialization from file
    • ice40_dsp - iCE40: map multipliers
    • ice40_opt - iCE40: perform simple optimizations
    • ice40_wrapcarry - iCE40: wrap carries
    • synth_ice40 - synthesis for iCE40 FPGAs
  • Intel (MAX10, Cyclone IV)
    • synth_intel - synthesis for Intel (Altera) FPGAs.
  • Intel ALM (Cyclone V, Arria V, Cyclone 10 GX)
    • synth_intel_alm - synthesis for ALM-based Intel (Altera) FPGAs.
  • Lattice
    • lattice_gsr - Lattice: handle GSR
    • synth_ecp5 - synthesis for ECP5 FPGAs
    • synth_lattice - synthesis for Lattice FPGAs
    • synth_nexus - synthesis for Nexus FPGAs
  • Microchip
    • microchip_dffopt - MICROCHIP: optimize FF control signal usage
    • microchip_dsp - MICROCHIP: pack resources into DSPs
    • synth_microchip - synthesis for Microchip FPGAs
  • Microchip - SmartFusion2/IGLOO2
    • synth_sf2 - synthesis for SmartFusion2 and IGLOO2 FPGAs
  • NanoXplore
    • nx_carry - NanoXplore: create carry cells
    • synth_nanoxplore - synthesis for NanoXplore FPGAs
  • QuickLogic
    • ql_bram_merge - Infers QuickLogic k6n10f BRAM pairs that can operate independently
    • ql_bram_types - Change TDP36K type to subtypes
    • ql_dsp_io_regs - change types of QL_DSP2 depending on configuration
    • ql_dsp_macc - infer QuickLogic multiplier-accumulator DSP cells
    • ql_dsp_simd - merge QuickLogic K6N10f DSP pairs to operate in SIMD mode
    • ql_ioff - Infer I/O FFs for qlf_k6n10f architecture
    • synth_quicklogic - Synthesis for QuickLogic FPGAs
  • Xilinx
    • synth_xilinx - synthesis for Xilinx FPGAs
    • xilinx_dffopt - Xilinx: optimize FF control signal usage
    • xilinx_dsp - Xilinx: pack resources into DSPs
    • xilinx_srl - Xilinx shift register extraction

• Internal commands for developers
  • example_dt - drivertools example
  • internal_stats - print internal statistics
  • test_abcloop - automatically test handling of loops in abc command
  • test_autotb - generate simple test benches
  • test_cell - automatically test the implementation of a cell type
  • test_generic - test the generic compute graph
  • test_pmgen - test pass for pmgen
• Writing command help
  • chformal - change formal constraints of the design
  • The formatted_help() method
  • Dumping command help to json
  • Command line rendering
  • RST generated from autocmd