Simulating circuits

eval - evaluate the circuit given an input

yosys> help eval
eval [options] [selection]
This command evaluates the value of a signal given the value of all required
inputs.
-set <signal> <value>
set the specified signal to the specified value.
-set-undef
set all unspecified source signals to undef (x)
-table <signal>
create a truth table using the specified input signals
-show <signal>
show the value for the specified signal. if no -show option is passed
then all output ports of the current module are used.

Note

Help text automatically generated from passes/sat/eval.cc:361

fst2tb - generate testbench out of fst file

yosys> help fst2tb
fst2tb [options] [top-level]
This command generates testbench for the circuit using the given top-level
module and simulus signal from FST file
-tb <name>
generated testbench name.
files <name>.v and <name>.txt are created as result.
-r <filename>
read simulation FST file
-clock <portname>
name of top-level clock input
-clockn <portname>
name of top-level clock input (inverse polarity)
-scope <name>
scope of simulation top model
-start <time>
start co-simulation in arbitary time (default 0)
-stop <time>
stop co-simulation in arbitary time (default END)
-n <integer>
number of clock cycles to simulate (default: 20)

Note

Help text automatically generated from passes/sat/sim.cc:2909

sim - simulate the circuit

yosys> help sim
sim [options] [top-level]
This command simulates the circuit using the given top-level module.
-vcd <filename>
write the simulation results to the given VCD file
-fst <filename>
write the simulation results to the given FST file
-aiw <filename>
write the simulation results to an AIGER witness file
(requires a *.aim file via -map)
-hdlname
use the hdlname attribute when writing simulation results
(preserves hierarchy in a flattened design)
-x
ignore constant x outputs in simulation file.
-date
include date and full version info in output.
-clock <portname>
name of top-level clock input
-clockn <portname>
name of top-level clock input (inverse polarity)
-multiclock
mark that witness file is multiclock.
-reset <portname>
name of top-level reset input (active high)
-resetn <portname>
name of top-level inverted reset input (active low)
-rstlen <integer>
number of cycles reset should stay active (default: 1)
-zinit
zero-initialize all uninitialized regs and memories
-timescale <string>
include the specified timescale declaration in the vcd
-n <integer>
number of clock cycles to simulate (default: 20)
-noinitstate
do not activate $initstate cells during the first cycle
-a
use all nets in VCD/FST operations, not just those with public names
-w
writeback mode: use final simulation state as new init state
-r <filename>
read simulation or formal results file
File formats supported: FST, VCD, AIW, WIT and .yw
VCD support requires vcd2fst external tool to be present
-width <integer>
cycle width in generated simulation output (must be divisible by 2).
-append <integer>
number of extra clock cycles to simulate for a Yosys witness input
-summary <filename>
write a JSON summary to the given file
-map <filename>
read file with port and latch symbols, needed for AIGER witness input
-scope <name>
scope of simulation top model
-at <time>
sets start and stop time
-start <time>
start co-simulation in arbitary time (default 0)
-stop <time>
stop co-simulation in arbitary time (default END)
-sim
simulation with stimulus from FST (default)
-sim-cmp
co-simulation expect exact match
-sim-gold
co-simulation, x in simulation can match any value in FST
-sim-gate
co-simulation, x in FST can match any value in simulation
-assert
fail the simulation command if, in the course of simulating,
any of the asserts in the design fail
-fst-noinit
do not initialize latches and memories from an input FST or VCD file
(use the initial defined by the design instead)
-q
disable per-cycle/sample log message
-d
enable debug output

Note

Help text automatically generated from passes/sat/sim.cc:2563