Unary operators

All unary RTL cells have one input port A and one output port Y. They also have the following parameters:

A_SIGNED

Set to a non-zero value if the input A is signed and therefore should be sign-extended when needed.

A_WIDTH

The width of the input port A.

Y_WIDTH

The width of the output port Y.

Table 4 Cell types for unary operators with their corresponding Verilog expressions.

Verilog

Cell Type

Y = ~A

$not

Y = +A

$pos

Y = -A

$neg

Y = &A

$reduce_and

Y = |A

$reduce_or

Y = ^A

$reduce_xor

Y = ~^A

$reduce_xnor

Y = |A

$reduce_bool

Y = !A

$logic_not

For the unary cells that output a logical value ($reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool, $logic_not), when the Y_WIDTH parameter is greater than 1, the output is zero-extended, and only the least significant bit varies.

Note that $reduce_or and $reduce_bool generally represent the same logic function. But the read_verilog frontend will generate them in different situations. A $reduce_or cell is generated when the prefix | operator is being used. A $reduce_bool cell is generated when a bit vector is used as a condition in an if-statement or ?:-expression.

yosys> help $buf

A simple coarse-grain buffer cell type for the experimental buffered-normalized mode. Note this cell does’t get removed by ‘opt_clean’ and is not recommended for general use.

Properties:

is_evaluable

Simulation model (verilog)
Listing 146 simlib.v
106module \$buf (A, Y);
107
108    parameter WIDTH = 0;
109
110    input [WIDTH-1:0] A;
111    output [WIDTH-1:0] Y;
112
113    assign Y = A;
114
115endmodule
yosys> help $logic_not

A logical inverter. This corresponds to the Verilog unary prefix ‘!’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 147 simlib.v
1521module \$logic_not (A, Y);
1522
1523    parameter A_SIGNED = 0;
1524    parameter A_WIDTH = 0;
1525    parameter Y_WIDTH = 0;
1526
1527    input [A_WIDTH-1:0] A;
1528    output [Y_WIDTH-1:0] Y;
1529
1530    generate
1531        if (A_SIGNED) begin:BLOCK1
1532            assign Y = !$signed(A);
1533        end else begin:BLOCK2
1534            assign Y = !A;
1535        end
1536    endgenerate
1537
1538endmodule
yosys> help $neg

An arithmetic inverter. This corresponds to the Verilog unary prefix ‘-’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 148 simlib.v
126module \$neg (A, Y);
127
128    parameter A_SIGNED = 0;
129    parameter A_WIDTH = 0;
130    parameter Y_WIDTH = 0;
131
132    input [A_WIDTH-1:0] A;
133    output [Y_WIDTH-1:0] Y;
134
135    generate
136        if (A_SIGNED) begin:BLOCK1
137            assign Y = -$signed(A);
138        end else begin:BLOCK2
139            assign Y = -A;
140        end
141    endgenerate
142
143endmodule
yosys> help $not

Bit-wise inverter

This corresponds to the Verilog unary prefix ‘~’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 149 simlib.v
48module \$not (A, Y);
49
50    parameter A_SIGNED = 0;
51    parameter A_WIDTH = 0;
52    parameter Y_WIDTH = 0;
53
54    input [A_WIDTH-1:0] A;
55    output [Y_WIDTH-1:0] Y;
56
57    generate
58        if (A_SIGNED) begin:BLOCK1
59            assign Y = ~$signed(A);
60        end else begin:BLOCK2
61            assign Y = ~A;
62        end
63    endgenerate
64
65endmodule
yosys> help $pos

A buffer. This corresponds to the Verilog unary prefix ‘+’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 150 simlib.v
76module \$pos (A, Y);
77
78    parameter A_SIGNED = 0;
79    parameter A_WIDTH = 0;
80    parameter Y_WIDTH = 0;
81
82    input [A_WIDTH-1:0] A;
83    output [Y_WIDTH-1:0] Y;
84
85    generate
86        if (A_SIGNED) begin:BLOCK1
87            assign Y = $signed(A);
88        end else begin:BLOCK2
89            assign Y = A;
90        end
91    endgenerate
92
93endmodule
yosys> help $reduce_and

An AND reduction. This corresponds to the Verilog unary prefix ‘&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 151 simlib.v
278module \$reduce_and (A, Y);
279
280    parameter A_SIGNED = 0;
281    parameter A_WIDTH = 0;
282    parameter Y_WIDTH = 0;
283
284    input [A_WIDTH-1:0] A;
285    output [Y_WIDTH-1:0] Y;
286
287    generate
288        if (A_SIGNED) begin:BLOCK1
289            assign Y = &$signed(A);
290        end else begin:BLOCK2
291            assign Y = &A;
292        end
293    endgenerate
294
295endmodule
yosys> help $reduce_bool

An OR reduction. This cell type is used instead of $reduce_or when a signal is implicitly converted to a boolean signal, e.g. for operands of ‘&&’ and ‘||’.

Properties:

is_evaluable

Simulation model (verilog)
Listing 152 simlib.v
391module \$reduce_bool (A, Y);
392
393    parameter A_SIGNED = 0;
394    parameter A_WIDTH = 0;
395    parameter Y_WIDTH = 0;
396
397    input [A_WIDTH-1:0] A;
398    output [Y_WIDTH-1:0] Y;
399
400    generate
401        if (A_SIGNED) begin:BLOCK1
402            assign Y = !(!$signed(A));
403        end else begin:BLOCK2
404            assign Y = !(!A);
405        end
406    endgenerate
407
408endmodule
yosys> help $reduce_or

An OR reduction. This corresponds to the Verilog unary prefix ‘|’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 153 simlib.v
306module \$reduce_or (A, Y);
307
308    parameter A_SIGNED = 0;
309    parameter A_WIDTH = 0;
310    parameter Y_WIDTH = 0;
311
312    input [A_WIDTH-1:0] A;
313    output [Y_WIDTH-1:0] Y;
314
315    generate
316        if (A_SIGNED) begin:BLOCK1
317            assign Y = |$signed(A);
318        end else begin:BLOCK2
319            assign Y = |A;
320        end
321    endgenerate
322
323endmodule
yosys> help $reduce_xnor

A XNOR reduction. This corresponds to the Verilog unary prefix ‘~^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 154 simlib.v
362module \$reduce_xnor (A, Y);
363
364    parameter A_SIGNED = 0;
365    parameter A_WIDTH = 0;
366    parameter Y_WIDTH = 0;
367
368    input [A_WIDTH-1:0] A;
369    output [Y_WIDTH-1:0] Y;
370
371    generate
372        if (A_SIGNED) begin:BLOCK1
373            assign Y = ~^$signed(A);
374        end else begin:BLOCK2
375            assign Y = ~^A;
376        end
377    endgenerate
378
379endmodule
yosys> help $reduce_xor

A XOR reduction. This corresponds to the Verilog unary prefix ‘^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 155 simlib.v
334module \$reduce_xor (A, Y);
335
336    parameter A_SIGNED = 0;
337    parameter A_WIDTH = 0;
338    parameter Y_WIDTH = 0;
339
340    input [A_WIDTH-1:0] A;
341    output [Y_WIDTH-1:0] Y;
342
343    generate
344        if (A_SIGNED) begin:BLOCK1
345            assign Y = ^$signed(A);
346        end else begin:BLOCK2
347            assign Y = ^A;
348        end
349    endgenerate
350
351endmodule