Passes¶
- Working with hierarchy
- Converting process blocks
- proc - translate processes to netlists
- proc_arst - detect asynchronous resets
- proc_clean - remove empty parts of processes
- proc_dff - extract flip-flops from processes
- proc_dlatch - extract latches from processes
- proc_init - convert initial block to init attributes
- proc_memwr - extract memory writes from processes
- proc_mux - convert decision trees to multiplexers
- proc_prune - remove redundant assignments
- proc_rmdead - eliminate dead trees in decision trees
- proc_rom - convert switches to ROMs
- FSM handling
- fsm - extract and optimize finite state machines
- fsm_detect - finding FSMs in design
- fsm_expand - expand FSM cells by merging logic into it
- fsm_export - exporting FSMs to KISS2 files
- fsm_extract - extracting FSMs in design
- fsm_info - print information on finite state machines
- fsm_map - mapping FSMs to basic logic
- fsm_opt - optimize finite state machines
- fsm_recode - recoding finite state machines
- Memory handling
- memory - translate memories to basic cells
- memory_bmux2rom - convert muxes to ROMs
- memory_bram - map memories to block rams
- memory_collect - creating multi-port memory cells
- memory_dff - merge input/output DFFs into memory read ports
- memory_libmap - map memories to cells
- memory_map - translate multiport memories to basic cells
- memory_memx - emulate vlog sim behavior for mem ports
- memory_narrow - split up wide memory ports
- memory_nordff - extract read port FFs from memories
- memory_share - consolidate memory ports
- memory_unpack - unpack multi-port memory cells
- Optimization passes
- clean - remove unused cells and wires
- muxpack - $mux/$pmux cascades to $pmux
- onehot - optimize $eq cells for onehot signals
- opt - perform simple optimizations
- opt_clean - remove unused cells and wires
- opt_demorgan - Optimize reductions with DeMorgan equivalents
- opt_dff - perform DFF optimizations
- opt_expr - perform const folding and simple expression rewriting
- opt_ffinv - push inverters through FFs
- opt_hier - perform cross-boundary optimization
- opt_lut - optimize LUT cells
- opt_lut_ins - discard unused LUT inputs
- opt_mem - optimize memories
- opt_mem_feedback - convert memory read-to-write port feedback paths to write enables
- opt_mem_priority - remove priority relations between write ports that can never collide
- opt_mem_widen - optimize memories where all ports are wide
- opt_merge - consolidate identical cells
- opt_muxtree - eliminate dead trees in multiplexer trees
- opt_reduce - simplify large MUXes and AND/OR gates
- opt_share - merge mutually exclusive cells of the same type that share an input signal
- peepopt - collection of peephole optimizers
- pmux2shiftx - transform $pmux cells to $shiftx cells
- recover_names - Execute a lossy mapping command and recover original netnames
- share - perform sat-based resource sharing
- wreduce - reduce the word size of operations if possible
- Technology mapping
- abc - use ABC for technology mapping
- abc9 - use ABC9 for technology mapping
- abc9_exe - use ABC9 for technology mapping
- abc9_ops - helper functions for ABC9
- abc_new - (experimental) use ABC for SC technology mapping (new)
- aigmap - map logic to and-inverter-graph circuit
- alumacc - extract ALU and MACC cells
- attrmap - renaming attributes
- attrmvcp - move or copy attributes from wires to driving cells
- bmuxmap - transform $bmux cells to trees of $mux cells
- booth - map $mul cells to Booth multipliers
- bufnorm - (experimental) convert design into buffered-normalized form
- bwmuxmap - replace $bwmux cells with equivalent logic
- cellmatch - match cells to their targets in cell library
- clkbufmap - insert clock buffers on clock networks
- clockgate - extract clock gating out of flip flops
- constmap - technology mapping of coarse constant value
- deminout - demote inout ports to input or output
- demuxmap - transform $demux cells to $eq + $mux cells
- dffinit - set INIT param on FF cells
- dfflegalize - convert FFs to types supported by the target
- dfflibmap - technology mapping of flip-flops
- dffunmap - unmap clock enable and synchronous reset from FFs
- extract - find subcircuits and replace them with cells
- extract_counter - Extract GreenPak4 counter cells
- extract_fa - find and extract full/half adders
- extract_reduce - converts gate chains into $reduce_* cells
- extractinv - extract explicit inverter cells for invertible cell pins
- flowmap - pack LUTs with FlowMap
- hilomap - technology mapping of constant hi- and/or lo-drivers
- insbuf - insert buffer cells for connected wires
- iopadmap - technology mapping of i/o pads (or buffers)
- libcache - control caching of technology library data parsed from liberty files
- lut2mux - convert $lut to $_MUX_
- maccmap - mapping macc cells
- muxcover - cover trees of MUX cells with wider MUXes
- nlutmap - map to LUTs of different sizes
- paramap - renaming cell parameters
- pmuxtree - transform $pmux cells to trees of $mux cells
- shregmap - map shift registers
- simplemap - mapping simple coarse-grain cells
- techmap - generic technology mapper
- tribuf - infer tri-state buffers
- zinit - add inverters so all FF are zero-initialized
- Design modification
- abstract - replace signals with abstract values during formal verification
- add - add objects to the design
- autoname - automatically assign names to objects
- blackbox - convert modules into blackbox modules
- box_derive - derive box modules
- bugpoint - minimize testcases
- chparam - re-evaluate modules with new parameters
- chtype - change type of cells in the design
- clean_zerowidth - clean zero-width connections from the design
- connect - create or remove connections
- connwrappers - match width of input-output port pairs
- copy - copy modules in the design
- delete - delete objects in the design
- design - save, restore and reset current design
- expose - convert internal signals to module ports
- linecoverage - report coverage information
- rename - rename object in the design
- scatter - add additional intermediate nets
- setattr - set/unset attributes on objects
- setparam - set/unset parameters on objects
- setundef - replace undef values with defined constants
- splice - create explicit splicing cells
- splitcells - split up multi-bit cells
- splitnets - split up multi-bit nets
- test_select - call internal selection methods on design for testing purposes
- timeest - estimate timing
- wbflip - flip the whitebox attribute
- wrapcell - wrap individual cells into new modules
- Equivalence checking
- equiv_add - add a $equiv cell
- equiv_induct - proving $equiv cells using temporal induction
- equiv_make - prepare a circuit for equivalence checking
- equiv_mark - mark equivalence checking regions
- equiv_miter - extract miter from equiv circuit
- equiv_opt - prove equivalence for optimized circuit
- equiv_purge - purge equivalence checking module
- equiv_remove - remove $equiv cells
- equiv_simple - try proving simple $equiv instances
- equiv_status - print status of equivalent checking module
- equiv_struct - structural equivalence checking
- Simulating circuits
- Design status
- cd - a shortcut for ‘select -module <name>’
- check - check for obvious problems in the design
- cover - print code coverage counters
- debug - run command with debug log messages enabled
- edgetypes - list all types of edges in selection
- exec - execute commands in the operating system shell
- log - print text and log files
- logger - set logger properties
- ls - list modules or objects in modules
- ltp - print longest topological path
- plugin - load and list loaded plugins
- portarcs - derive port arcs for propagation delay
- portlist - list (top-level) ports
- printattrs - print attributes of selected objects
- scc - detect strongly connected components (logic loops)
- scratchpad - get/set values in the scratchpad
- select - modify and view the list of selected objects
- setenv - set an environment variable
- show - generate schematics using graphviz
- sta - perform static timing analysis
- stat - print some statistics
- tee - redirect command output to file
- torder - print cells in topological order
- trace - redirect command output to file
- viz - visualize data flow graph
- write_file - write a text to a file