Technology mapping¶

abc - use ABC for technology mapping¶

yosys> help abc¶

abc [options] [selection]¶

This pass uses the ABC tool [1] for technology mapping of yosys's internal gate
library to a target architecture.

-exe <command>

use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
This can e.g. be used to call a specific version of ABC or a wrapper.

-script <file>

use the specified ABC script file instead of the default script.

if <file> starts with a plus sign (+), then the rest of the filename
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.

if no -script parameter is given, the following scripts are used:

for -liberty/-genlib without -constr:
strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
&get -n; &dch -f; &nf {D}; &put

for -liberty/-genlib with -constr:
strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
&get -n; &dch -f; &nf {D}; &put; buffer; upsize {D};
dnsize {D}; stime -p

for -lut/-luts (only one LUT size):
strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
dch -f; if; mfs2; lutpack {S}

for -lut/-luts (different LUT sizes):
strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
dch -f; if; mfs2

for -sop:
strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
dch -f; cover {I} {P}

otherwise:
strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
&get -n; &dch -f; &nf {D}; &put

-fast

use different default scripts that are slightly faster (at the cost
of output quality):

for -liberty/-genlib without -constr:
strash; dretime; map {D}

for -liberty/-genlib with -constr:
strash; dretime; map {D}; buffer; upsize {D}; dnsize {D};
stime -p

for -lut/-luts:
strash; dretime; if

for -sop:
strash; dretime; cover {I} {P}

otherwise:
strash; dretime; map

-liberty <file>

generate netlists for the specified cell library (using the liberty
file format).

-dont_use <cell_name>

generate netlists for the specified cell library (using the liberty
file format).

-genlib <file>

generate netlists for the specified cell library (using the SIS Genlib
file format).

-constr <file>

pass this file with timing constraints to ABC.
use with -liberty/-genlib.

a constr file contains two lines:
set_driving_cell <cell_name>
set_load <floating_point_number>

the set_driving_cell statement defines which cell type is assumed to
drive the primary inputs and the set_load statement sets the load in
femtofarads for each primary output.

-D <picoseconds>

set delay target. the string {D} in the default scripts above is
replaced by this option when used, and an empty string otherwise.
this also replaces 'dretime' with 'dretime; retime -o {D}' in the
default scripts above.

-I <num>

maximum number of SOP inputs.
(replaces {I} in the default scripts above)

-P <num>

maximum number of SOP products.
(replaces {P} in the default scripts above)

-S <num>

maximum number of LUT inputs shared.
(replaces {S} in the default scripts above, default: -S 1)

-lut <width>

generate netlist using luts of (max) the specified width.

-lut <w1>:<w2>

generate netlist using luts of (max) the specified width <w2>. All
luts with width <= <w1> have constant cost. for luts larger than <w1>
the area cost doubles with each additional input bit. the delay cost
is still constant for all lut widths.

-luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..

generate netlist using luts. Use the specified costs for luts with 1,
2, 3, .. inputs.

-sop

map to sum-of-product cells and inverters

-g type1,type2,...

Map to the specified list of gate types. Supported gates types are:
AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,
NMUX, AOI3, OAI3, AOI4, OAI4.
(The NOT gate is always added to this list automatically.)

The following aliases can be used to reference common sets of gate
types:
simple: AND OR XOR MUX
cmos2:  NAND NOR
cmos3:  NAND NOR AOI3 OAI3
cmos4:  NAND NOR AOI3 OAI3 AOI4 OAI4
cmos:   NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR
gates:  AND NAND OR NOR XOR XNOR ANDNOT ORNOT
aig:    AND NAND OR NOR ANDNOT ORNOT

The alias 'all' represent the full set of all gate types.

Prefix a gate type with a '-' to remove it from the list. For example
the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.

The default is 'all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4'.

-dff

also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
clock domains are automatically partitioned in clock domains and each
domain is passed through ABC independently.

-clk [!]<clock-signal-name>[,[!]<enable-signal-name>]

use only the specified clock domain. this is like -dff, but only FF
cells that belong to the specified clock domain are used.

-keepff

set the "keep" attribute on flip-flop output wires. (and thus preserve
them, for example for equivalence checking.)

-nocleanup

when this option is used, the temporary files created by this pass
are not removed. this is useful for debugging.

-showtmp

print the temp dir name in log. usually this is suppressed so that the
command output is identical across runs.

-markgroups

set a 'abcgroup' attribute on all objects created by ABC. The value of
this attribute is a unique integer for each ABC process started. This
is useful for debugging the partitioning of clock domains.

-dress

run the 'dress' command after all other ABC commands. This aims to
preserve naming by an equivalence check between the original and
post-ABC netlists (experimental).

When no target cell library is specified the Yosys standard cell library is
loaded into ABC before the ABC script is executed.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write_blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/

Note

Help text automatically generated from passes/techmap/abc.cc:1571

abc9 - use ABC9 for technology mapping¶

yosys> help abc9¶

abc9 [options] [selection]¶

This script pass performs a sequence of commands to facilitate the use of the
ABC tool [1] for technology mapping of the current design to a target FPGA
architecture. Only fully-selected modules are supported.

-run <from_label>:<to_label>

only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.

-exe <command>

use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
This can e.g. be used to call a specific version of ABC or a wrapper.

-script <file>

use the specified ABC script file instead of the default script.

if <file> starts with a plus sign (+), then the rest of the filename
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.

if no -script parameter is given, the following scripts are used:
&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs

-fast

use different default scripts that are slightly faster (at the cost
of output quality):
&if {C} {W} {D} {R} -v

-D <picoseconds>

set delay target. the string {D} in the default scripts above is
replaced by this option when used, and an empty string otherwise
(indicating best possible delay).

-lut <width>

generate netlist using luts of (max) the specified width.

-lut <w1>:<w2>

generate netlist using luts of (max) the specified width <w2>. All
luts with width <= <w1> have constant cost. for luts larger than <w1>
the area cost doubles with each additional input bit. the delay cost
is still constant for all lut widths.

-lut <file>

pass this file with lut library to ABC.

-luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..

generate netlist using luts. Use the specified costs for luts with 1,
2, 3, .. inputs.

-maxlut <width>

when auto-generating the lut library, discard all luts equal to or
greater than this size (applicable when neither -lut nor -luts is
specified).

-dff

also pass $_DFF_[NP]_ cells through to ABC. modules with many clock
domains are supported and automatically partitioned by ABC.

-nocleanup

when this option is used, the temporary files created by this pass
are not removed. this is useful for debugging.

-showtmp

print the temp dir name in log. usually this is suppressed so that the
command output is identical across runs.

-box <file>

pass this file with box library to ABC.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as an XAIGER file with `write_xaiger' and then load that into ABC
externally if you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/

    check:
        abc9_ops -check [-dff]    (option if -dff)

    map:
        abc9_ops -prep_hier [-dff]    (option if -dff)
        scc -specify -set_attr abc9_scc_id {}
        abc9_ops -prep_bypass [-prep_dff]    (option if -dff)
        design -stash $abc9
        design -load $abc9_map
        select =*
        wbflip
        techmap -autoproc -wb -map %$abc9 -map +/techmap.v A:abc9_flop
        opt -nodffe -nosdff
        abc9_ops -prep_dff_submod                                                     (only if -dff)
        setattr -set submod "$abc9_flop" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d           (only if -dff)
        submod                                                                        (only if -dff)
        setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop    (only if -dff)
        foreach module in design
            rename <module-name>_$abc9_flop _TECHMAP_REPLACE_                         (only if -dff)
        abc9_ops -prep_dff_unmap                                                      (only if -dff)
        design -copy-to $abc9 =*_$abc9_flop                                           (only if -dff)
        delete =*_$abc9_flop                                                          (only if -dff)
        design -stash $abc9_map
        design -load $abc9
        design -delete $abc9
        techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v [-D DFF]    (option if -dff)
        design -delete $abc9_map

    pre:
        read_verilog -icells -lib -specify +/abc9_model.v
        abc9_ops -break_scc -prep_delays -prep_xaiger [-dff]    (option for -dff)
        abc9_ops -prep_lut <maxlut>    (skip if -lut or -luts)
        abc9_ops -prep_box    (skip if -box)
        design -stash $abc9
        design -load $abc9_holes
        select =*
        techmap -wb -map %$abc9 -map +/techmap.v
        opt -purge
        aigmap
        design -stash $abc9_holes
        design -load $abc9
        design -delete $abc9

    exe:
        aigmap
        foreach module in selection
            abc9_ops -write_lut <abc-temp-dir>/input.lut    (skip if '-lut' or '-luts')
            abc9_ops -write_box <abc-temp-dir>/input.box    (skip if '-box')
            write_xaiger -map <abc-temp-dir>/input.sym [-dff] <abc-temp-dir>/input.xaig
            abc9_exe [options] -cwd <abc-temp-dir> -lut [<abc-temp-dir>/input.lut] -box [<abc-temp-dir>/input.box]
            read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig
            abc9_ops -reintegrate [-dff]

    unmap:
        techmap -wb -map %$abc9_unmap -map +/abc9_unmap.v
        design -delete $abc9_unmap
        design -delete $abc9_holes
        delete =*_$abc9_byp
        setattr -mod -unset abc9_box_id

Note

Help text automatically generated from passes/techmap/abc9.cc:38

abc9_exe - use ABC9 for technology mapping¶

yosys> help abc9_exe¶

abc9_exe [options]¶

This pass uses the ABC tool [1] for technology mapping of the top module
(according to the (* top *) attribute or if only one module is currently
selected) to a target FPGA architecture.

-exe <command>

use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
This can e.g. be used to call a specific version of ABC or a wrapper.

-script <file>

use the specified ABC script file instead of the default script.

if <file> starts with a plus sign (+), then the rest of the filename
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.

if no -script parameter is given, the following scripts are used:
&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs

-fast

use different default scripts that are slightly faster (at the cost
of output quality):
&if {C} {W} {D} {R} -v

-constr <file>

pass this file with timing constraints to ABC.
use with -liberty.

a constr file contains two lines:
set_driving_cell <cell_name>
set_load <floating_point_number>

the set_driving_cell statement defines which cell type is assumed to
drive the primary inputs and the set_load statement sets the load in
femtofarads for each primary output.

-liberty <file>

read the given Liberty file as a description of the target cell library.
this option can be used multiple times.

-genlib <file>

read the given genlib file as a description of the target cell library.
this option can be used multiple times.

-dont_use <cell_name>

avoid usage of the technology cell <cell_name> when mapping the design.
this option can be used multiple times. only supported with Liberty
cell libraries.

-D <picoseconds>

set delay target. the string {D} in the default scripts above is
replaced by this option when used, and an empty string otherwise
(indicating best possible delay).

-lut <width>

generate netlist using luts of (max) the specified width.

-lut <w1>:<w2>

generate netlist using luts of (max) the specified width <w2>. All
luts with width <= <w1> have constant cost. for luts larger than <w1>
the area cost doubles with each additional input bit. the delay cost
is still constant for all lut widths.

-lut <file>

pass this file with lut library to ABC.

-luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..

generate netlist using luts. Use the specified costs for luts with 1,
2, 3, .. inputs.

-showtmp

print the temp dir name in log. usually this is suppressed so that the
command output is identical across runs.

-box <file>

pass this file with box library to ABC.

-cwd <dir>

use this as the current working directory, inside which the 'input.xaig'
file is expected. temporary files will be created in this directory, and
the mapped result will be written to 'output.aig'.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write_blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/

Note

Help text automatically generated from passes/techmap/abc9_exe.cc:339

abc9_ops - helper functions for ABC9¶

yosys> help abc9_ops¶

abc9_ops [options] [selection]¶

This pass contains a set of supporting operations for use during ABC technology
mapping, and is expected to be called in conjunction with other operations from
the `abc9' script pass. Only fully-selected modules are supported.

-check

check that the design is valid, e.g. (* abc9_box_id *) values are
unique, (* abc9_carry *) is only given for one input/output port, etc.

-prep_hier

derive all used (* abc9_box *) or (* abc9_flop *) (if -dff option)
whitebox modules. with (* abc9_flop *) modules, only those containing
$dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC
limitation -- will be derived.

-prep_bypass

create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for
bypassing sequential (* abc9_box *) modules using a combinatorial box
(named *_$abc9_byp). bypassing is necessary if sequential elements (e.g.
$dff, $mem, etc.) are discovered inside so that any combinatorial paths
will be correctly captured. this bypass box will only contain ports that
are referenced by a simple path declaration ($specify2 cell) inside a
specify block.

-prep_dff

select all (* abc9_flop *) modules instantiated in the design and store
in the named selection '$abc9_flops'.

-prep_dff_submod

within (* abc9_flop *) modules, rewrite all edge-sensitive path
declarations and $setup() timing checks ($specify3 and $specrule cells)
that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port
to the DFF's 'D' port. this is to prepare such specify cells to be moved
into the flop box.

-prep_dff_unmap

populate the '$abc9_unmap' design with techmap rules for mapping
*_$abc9_flop cells back into their derived cell types (where the rules
created by -prep_hier will then map back to the original cell with
parameters).

-prep_delays

insert `$__ABC9_DELAY' blackbox cells into the design to account for
certain required times.

-break_scc

for an arbitrarily chosen cell in each unique SCC of each selected
module (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt
all wires driven by this cell's outputs with a temporary
$__ABC9_SCC_BREAKER cell to break the SCC.

-prep_xaiger

prepare the design for XAIGER output. this includes computing the
topological ordering of ABC9 boxes, as well as preparing the
'$abc9_holes' design that contains the logic behaviour of ABC9
whiteboxes.

-dff

consider flop cells (those instantiating modules marked with
(* abc9_flop *)) during -prep_{delays,xaiger,box}.

-prep_lut <maxlut>

pre-compute the lut library by analysing all modules marked with
(* abc9_lut=<area> *).

-write_lut <dst>

write the pre-computed lut library to <dst>.

-prep_box

pre-compute the box library by analysing all modules marked with
(* abc9_box *).

-write_box <dst>

write the pre-computed box library to <dst>.

-reintegrate

for each selected module, re-intergrate the module '<module-name>$abc9'
by first recovering ABC9 boxes, and then stitching in the remaining
primary inputs and outputs.

Note

Help text automatically generated from passes/techmap/abc9_ops.cc:1567

abc_new - (experimental) use ABC for SC technology mapping (new)¶

yosys> help abc_new¶

Warning

This command is experimental

abc_new [options] [selection]¶

This command uses the ABC tool [1] to optimize the current design and map it to
the target standard cell library.

-run <from_label>:<to_label>

only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.

-exe <command>

-script <file>

-D <picoseconds>

-constr <file>

-dont_use <cell_name>

-liberty <file>

-genlib <file>

these options are passed on to the 'abc9_exe' command which invokes
the ABC tool on individual modules of the design. please see
'help abc9_exe' for more details

[1] http://www.eecs.berkeley.edu/~alanmi/abc/

    check:
        abc9_ops -check

    prep_boxes:
        box_derive
        abc9_ops -prep_box

    map:
        foreach module in selection
          abc9_ops -write_box <abc-temp-dir>/input.box
          write_xaiger2 -mapping_prep -map2 <abc-temp-dir>/input.map2 <abc-temp-dir>/input.xaig
          abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box
          read_xaiger2 -sc_mapping -module_name <module> -map2 <abc-temp-dir>/input.map2 <abc-temp-dir>/output.aig

Note

Help text automatically generated from passes/techmap/abc_new.cc:46

aigmap - map logic to and-inverter-graph circuit¶

yosys> help aigmap¶

aigmap [options] [selection]¶

Replace all logic cells with circuits made of only $_AND_ and
$_NOT_ cells.

-nand

Enable creation of $_NAND_ cells

-select

Overwrite replaced cells in the current selection with new $_AND_,
$_NOT_, and $_NAND_, cells

Note

Help text automatically generated from passes/techmap/aigmap.cc:27

alumacc - extract ALU and MACC cells¶

yosys> help alumacc¶

alumacc [selection]¶

This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu
and $macc cells.

Note

Help text automatically generated from passes/techmap/alumacc.cc:562

attrmap - renaming attributes¶

yosys> help attrmap¶

attrmap [options] [selection]¶

This command renames attributes and/or maps key/value pairs to
other key/value pairs.

-tocase <name>

Match attribute names case-insensitively and set it to the specified
name.

-rename <old_name> <new_name>

Rename attributes as specified

-map <old_name>=<old_value> <new_name>=<new_value>

Map key/value pairs as indicated.

-imap <old_name>=<old_value> <new_name>=<new_value>

Like -map, but use case-insensitive match for <old_value> when
it is a string value.

-remove <name>=<value>

Remove attributes matching this pattern.

-modattr

Operate on module attributes instead of attributes on wires and cells.

For example, mapping Xilinx-style "keep" attributes to Yosys-style:

    attrmap -tocase keep -imap keep="true" keep=1 \

-imap keep="false" keep=0 -remove keep=0

Note

Help text automatically generated from passes/techmap/attrmap.cc:223

attrmvcp - move or copy attributes from wires to driving cells¶

yosys> help attrmvcp¶

attrmvcp [options] [selection]¶

Move or copy attributes on wires to the cells driving them.

-copy

By default, attributes are moved. This will only add
the attribute to the cell, without removing it from
the wire.

-purge

If no selected cell consumes the attribute, then it is
left on the wire by default. This option will cause the
attribute to be removed from the wire, even if no selected
cell takes it.

-driven

By default, attriburtes are moved to the cell driving the
wire. With this option set it will be moved to the cell
driven by the wire instead.

-attr <attrname>

Move or copy this attribute. This option can be used
multiple times.

Note

Help text automatically generated from passes/techmap/attrmvcp.cc:27

bmuxmap - transform $bmux cells to trees of $mux cells¶

yosys> help bmuxmap¶

bmuxmap [selection]¶

This pass transforms $bmux cells to trees of $mux cells.

-pmux

transform to $pmux instead of $mux cells.

Note

Help text automatically generated from passes/techmap/bmuxmap.cc:27

booth - map $mul cells to Booth multipliers¶

yosys> help booth¶

booth [selection]¶

This pass replaces multiplier cells with a radix-4 Booth-encoded implementation.
It operates on $mul cells whose width of operands is at least 4x4 and whose
width of result is at least 8.

-lowpower

use an alternative low-power architecture for the generated multiplier
(signed multipliers only)

Note

Help text automatically generated from passes/techmap/booth.cc:1159

bufnorm - (experimental) convert design into buffered-normalized form¶

yosys> help bufnorm¶

Warning

This command is experimental

bufnorm [options] [selection]¶

Insert buffer cells into the design as needed, to make sure that each wire
has exactly one driving cell port, and aliasing wires are buffered using
buffer cells, than can be chained in a canonical order.

Running 'bufnorm' on the whole design enters 'buffered-normalized mode'.

-buf

Create $buf cells for all buffers. The default is to use $_BUF_ cells
for sigle-bit buffers and $buf cells only for multi-bit buffers.

-chain

Chain all alias wires. By default only wires with positive-valued
'chain' or 'keep' attribute on them are chained.

-output

Enable chaining of ouput ports wires.

-public

Enable chaining of wires wth public names.

-nochain

Disable chaining of wires with 'chain' attribute.

-nokeep

Disable chaining of wires with 'keep' attribute.

-flat

Alias for -nokeep and -nochain.

-nosticky

Disable 'sticky' behavior of output ports already driving whole
wires, and always enforce canonical sort order instead.

-alphasort

Strictly use alphanumeric sort for chain-order. (Default is
to chain 'keep' wires first, then ports in declaration order,
and then the other wires in alphanumeric sort order.)

Run 'bufnorm' with -pos, -bits, or -conn on the whole design to remove all
$buf buffer cells and exit 'buffered-normalized mode' again.

-pos

Create (multi- and single-bit) $pos cells instead $buf and $_BUF_.

-bits

Create arrays of $_BUF_ cells instead of multi-bit $buf cells.

-conn

Create 'direct connections' instead of buffer cells.

-nomode

Do not automatically enter or leave 'buffered-normalized mode'.

The 'bufnorm' command can also be used to just switch in and out of
'buffered-normalized mode' and run the low-level re-normalizer.

-update

Enter 'buffered-normalized mode' and (re-)normalize.

-reset

Leave 'buffered-normalized mode' without changing the netlist.

Note

Help text automatically generated from passes/techmap/bufnorm.cc:27

bwmuxmap - replace $bwmux cells with equivalent logic¶

yosys> help bwmuxmap¶

bwmxumap [options] [selection]

This pass replaces $bwmux cells with equivalent logic

Note

Help text automatically generated from passes/techmap/bwmuxmap.cc:26

cellmatch - match cells to their targets in cell library¶

yosys> help cellmatch¶

cellmatch -lib <design> [module selection]¶

This pass identifies functionally equivalent counterparts between each of the
selected modules and a module from the secondary design <design>. For every such
correspondence found, a techmap rule is generated for mapping instances of the
former to instances of the latter. This techmap rule is saved in yet another
design called '$cellmatch', which is created if non-existent.

This pass restricts itself to combinational modules. Modules are functionally
equivalent as long as their truth tables are identical upto a permutation of
inputs and outputs. The supported number of inputs is limited to 6.

    cellmatch -derive_luts [module selection]

For every port in each selected module, characterize its combinational
function with a 'lut' attribute if possible.

Note

Help text automatically generated from passes/techmap/cellmatch.cc:141

clkbufmap - insert clock buffers on clock networks¶

yosys> help clkbufmap¶

clkbufmap [options] [selection]¶

Inserts clock buffers between nets connected to clock inputs and their drivers.

In the absence of any selection, all wires without the 'clkbuf_inhibit'
attribute will be considered for clock buffer insertion.
Alternatively, to consider all wires without the 'buffer_type' attribute set to
'none' or 'bufr' one would specify:
  'w:* a:buffer_type=none a:buffer_type=bufr %u %d'
as the selection.

-buf <celltype> <portname_out>:<portname_in>

Specifies the cell type to use for the clock buffers
and its port names.  The first port will be connected to
the clock network sinks, and the second will be connected
to the actual clock source.

-inpad <celltype> <portname_out>:<portname_in>

If specified, a PAD cell of the given type is inserted on
clock nets that are also top module's inputs (in addition
to the clock buffer, if any).

At least one of -buf or -inpad should be specified.

Note

Help text automatically generated from passes/techmap/clkbufmap.cc:37

clockgate - extract clock gating out of flip flops¶

yosys> help clockgate¶

clockgate [options] [selection]¶

This pass transforms each set of FFs sharing the same clock and
enable signal into a clock-gating cell and a set of enable-less FFs.
Primarily a power-saving transformation on ASIC designs.

-pos <celltype> <ce>:<clk>:<gclk>

If specified, rising-edge FFs will have CE inputs
removed and a gated clock will be created by the
user-specified <celltype> ICG (integrated clock gating)
cell with ports named <ce>, <clk>, <gclk>.
The ICG's clock enable pin must be active high.

-neg <celltype> <ce>:<clk>:<gclk>

If specified, falling-edge FFs will have CE inputs
removed and a gated clock will be created by the
user-specified <celltype> ICG (integrated clock gating)
cell with ports named <ce>, <clk>, <gclk>.
The ICG's clock enable pin must be active high.

-liberty <filename>

If specified, ICGs will be selected from the liberty files
if available. Priority is given to cells with fewer tie_lo
inputs and smaller size. This removes the need to manually
specify -pos or -neg and -tie_lo.

-dont_use <celltype>

Cells <celltype> won't be considered when searching for ICGs
in the liberty file specified by -liberty.

-tie_lo <port_name>

Port <port_name> of the ICG will be tied to zero.
Intended for DFT scan-enable pins.

-min_net_size <n>

Only transform sets of at least <n> eligible FFs.

Note

Help text automatically generated from passes/techmap/clockgate.cc:190

constmap - technology mapping of coarse constant value¶

yosys> help constmap¶

constmap [options] [selection]¶

Map constants to a driver cell.

-cell <celltype> <portname> <paramname>

Replace constant bits with this cell.
The value of the constant will be stored to the parameter specified.

Note

Help text automatically generated from passes/techmap/constmap.cc:44

deminout - demote inout ports to input or output¶

yosys> help deminout¶

deminout [options] [selection]¶

"Demote" inout ports to input or output ports, if possible.

Note

Help text automatically generated from passes/techmap/deminout.cc:27

demuxmap - transform $demux cells to $eq + $mux cells¶

yosys> help demuxmap¶

demuxmap [selection]¶

This pass transforms $demux cells to a bunch of equality comparisons.

Note

Help text automatically generated from passes/techmap/demuxmap.cc:27

dffinit - set INIT param on FF cells¶

yosys> help dffinit¶

dffinit [options] [selection]¶

This pass sets an FF cell parameter to the the initial value of the net it
drives. (This is primarily used in FPGA flows.)

-ff <cell_name> <output_port> <init_param>

operate on the specified cell type. this option can be used
multiple times.

-highlow

use the string values "high" and "low" to represent a single-bit
initial value of 1 or 0. (multi-bit values are not supported in this
mode.)

-strinit <string for high> <string for low>

use string values in the command line to represent a single-bit
initial value of 1 or 0. (multi-bit values are not supported in this
mode.)

-noreinit

fail if the FF cell has already a defined initial value set in other
passes and the initial value of the net it drives is not equal to
the already defined initial value.

Note

Help text automatically generated from passes/techmap/dffinit.cc:28

dfflegalize - convert FFs to types supported by the target¶

yosys> help dfflegalize¶

dfflegalize [options] [selection]¶

Converts FFs to types supported by the target.

-cell <cell_type_pattern> <init_values>

specifies a supported group of FF cells.  <cell_type_pattern>
is a yosys internal fine cell name, where ? characters can be
as a wildcard matching any character.  <init_values> specifies
which initialization values these FF cells can support, and can
be one of:

- x (no init value supported)
- 0
- 1
- r (init value has to match reset value, only for some FF types)
- 01 (both 0 and 1 supported).

-mince <num>

specifies a minimum number of FFs that should be using any given
clock enable signal.  If a clock enable signal doesn't meet this
threshold, it is unmapped into soft logic.

-minsrst <num>

specifies a minimum number of FFs that should be using any given
sync set/reset signal.  If a sync set/reset signal doesn't meet this
threshold, it is unmapped into soft logic.

The following cells are supported by this pass (ie. will be ingested,
and can be specified as allowed targets):

- $_DFF_[NP]_
- $_DFFE_[NP][NP]_
- $_DFF_[NP][NP][01]_
- $_DFFE_[NP][NP][01][NP]_
- $_ALDFF_[NP][NP]_
- $_ALDFFE_[NP][NP][NP]_
- $_DFFSR_[NP][NP][NP]_
- $_DFFSRE_[NP][NP][NP][NP]_
- $_SDFF_[NP][NP][01]_
- $_SDFFE_[NP][NP][01][NP]_
- $_SDFFCE_[NP][NP][01][NP]_
- $_SR_[NP][NP]_
- $_DLATCH_[NP]_
- $_DLATCH_[NP][NP][01]_
- $_DLATCHSR_[NP][NP][NP]_

The following transformations are performed by this pass:

- upconversion from a less capable cell to a more capable cell, if the less
  capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)
- unmapping FFs with clock enable (due to unsupported cell type or -mince)
- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)
- adding inverters on the control pins (due to unsupported polarity)
- adding inverters on the D and Q pins and inverting the init/reset values
  (due to unsupported init or reset value)
- converting sr into adlatch (by tying D to 1 and using E as set input)
- emulating unsupported dffsr cell by adff + adff + sr + mux
- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux
- emulating adff when the (reset, init) value combination is unsupported by
  dff + adff + dlatch + mux
- emulating adlatch when the (reset, init) value combination is unsupported by
- dlatch + adlatch + dlatch + mux
If the pass is unable to realize a given cell type (eg. adff when only plain dff
is available), an error is raised.

Note

Help text automatically generated from passes/techmap/dfflegalize.cc:70

dfflibmap - technology mapping of flip-flops¶

yosys> help dfflibmap¶

dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]¶

Map internal flip-flop cells to the flip-flop cells in the technology
library specified in the given liberty files.

This pass may add inverters as needed. Therefore it is recommended to
first run this pass and then map the logic paths to the target technology.

When called with -prepare, this command will convert the internal FF cells
to the internal cell types that best match the cells found in the given
liberty file, but won't actually map them to the target cells.

When called with -map-only, this command will only map internal cell
types that are already of exactly the right type to match the target
cells, leaving remaining internal cells untouched.

When called with -info, this command will only print the target cell
list, along with their associated internal cell types, and the arguments
that would be passed to the dfflegalize pass.  The design will not be
changed.

When called with -dont_use, this command will not map to the specified cell
name as an alternative to setting the dont_use property in the Liberty file.
This argument can be called multiple times with different cell names. This
argument also supports simple glob patterns in the cell name.

Note

Help text automatically generated from passes/techmap/dfflibmap.cc:564

dffunmap - unmap clock enable and synchronous reset from FFs¶

yosys> help dffunmap¶

dffunmap [options] [selection]¶

This pass transforms FF types with clock enable and/or synchronous reset into
their base type (with neither clock enable nor sync reset) by emulating the
clock enable and synchronous reset with multiplexers on the cell input.

-ce-only

unmap only clock enables, leave synchronous resets alone.

-srst-only

unmap only synchronous resets, leave clock enables alone.

Note

Help text automatically generated from passes/techmap/dffunmap.cc:28

extract - find subcircuits and replace them with cells¶

yosys> help extract¶

extract -map <map_file> [options] [selection]¶

extract -mine <out_file> [options] [selection]¶

This pass looks for subcircuits that are isomorphic to any of the modules
in the given map file and replaces them with instances of this modules. The
map file can be a Verilog source file (*.v) or an RTLIL source file (*.il).

-map <map_file>

use the modules in this file as reference. This option can be used
multiple times.

-map %<design-name>

use the modules in this in-memory design as reference. This option can
be used multiple times.

-verbose

print debug output while analyzing

-constports

also find instances with constant drivers. this may be much
slower than the normal operation.

-nodefaultswaps

normally builtin port swapping rules for internal cells are used per
default. This turns that off, so e.g. 'a^b' does not match 'b^a'
when this option is used.

-compat <needle_type> <haystack_type>

Per default, the cells in the map file (needle) must have the
type as the cells in the active design (haystack). This option
can be used to register additional pairs of types that should
match. This option can be used multiple times.

-swap <needle_type> <port1>,<port2>[,...]

Register a set of swappable ports for a needle cell type.
This option can be used multiple times.

-perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]

Register a valid permutation of swappable ports for a needle
cell type. This option can be used multiple times.

-cell_attr <attribute_name>

Attributes on cells with the given name must match.

-wire_attr <attribute_name>

Attributes on wires with the given name must match.

-ignore_parameters

Do not use parameters when matching cells.

-ignore_param <cell_type> <parameter_name>

Do not use this parameter when matching cells.

This pass does not operate on modules with unprocessed processes in it.
(I.e. the 'proc' pass should be used first to convert processes to netlists.)

This pass can also be used for mining for frequent subcircuits. In this mode
the following options are to be used instead of the -map option.

-mine <out_file>

mine for frequent subcircuits and write them to the given RTLIL file

-mine_cells_span <min> <max>

only mine for subcircuits with the specified number of cells
default value: 3 5

-mine_min_freq <num>

only mine for subcircuits with at least the specified number of matches
default value: 10

-mine_limit_matches_per_module <num>

when calculating the number of matches for a subcircuit, don't count
more than the specified number of matches per module

-mine_max_fanout <num>

don't consider internal signals with more than <num> connections

The modules in the map file may have the attribute 'extract_order' set to an
integer value. Then this value is used to determine the order in which the pass
tries to map the modules to the design (ascending, default value is 0).

See 'help techmap' for a pass that does the opposite thing.

Note

Help text automatically generated from passes/techmap/extract.cc:348

extract_counter - Extract GreenPak4 counter cells¶

yosys> help extract_counter¶

extract_counter [options] [selection]¶

This pass converts non-resettable or async resettable counters to counter cells.
Use a target-specific 'techmap' map file to convert those cells to the actual
target cells.

-maxwidth N

Only extract counters up to N bits wide (default 64)

-minwidth N

Only extract counters at least N bits wide (default 2)

-allow_arst yes|no

Allow counters to have async reset (default yes)

-dir up|down|both

Look for up-counters, down-counters, or both (default down)

-pout X,Y,...

Only allow parallel output from the counter to the listed cell types
(if not specified, parallel outputs are not restricted)

Note

Help text automatically generated from passes/techmap/extract_counter.cc:760

extract_fa - find and extract full/half adders¶

yosys> help extract_fa¶

extract_fa [options] [selection]¶

This pass extracts full/half adders from a gate-level design.

-fa, -ha

Enable cell types (fa=full adder, ha=half adder)
All types are enabled if none of this options is used

-d <int>

Set maximum depth for extracted logic cones (default=20)

-b <int>

Set maximum breadth for extracted logic cones (default=6)

-v

Verbose output

Note

Help text automatically generated from passes/techmap/extract_fa.cc:542

extract_reduce - converts gate chains into $reduce_* cells¶

yosys> help extract_reduce¶

extract_reduce [options] [selection]¶

converts gate chains into $reduce_* cells

This command finds chains of $_AND_, $_OR_, and $_XOR_ cells and replaces them
with their corresponding $reduce_* cells. Because this command only operates on
these cell types, it is recommended to map the design to only these cell types
using the `abc -g` command. Note that, in some cases, it may be more effective
to map the design to only $_AND_ cells, run extract_reduce, map the remaining
parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.

-allow-off-chain

Allows matching of cells that have loads outside the chain. These cells
will be replicated and folded into the $reduce_* cell, but the original
cell will remain, driving its original loads.

Note

Help text automatically generated from passes/techmap/extract_reduce.cc:35

extractinv - extract explicit inverter cells for invertible cell pins¶

yosys> help extractinv¶

extractinv [options] [selection]¶

Searches the design for all cells with invertible pins controlled by a cell
parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.
If the parameter was set to 1, inserts an explicit inverter cell in front of
the pin instead.  Normally used for output to ISE, which does not support the
inversion parameters.

To mark a cell port as invertible, use (* invertible_pin = "param_name" *)
on the wire in the blackbox module.  The parameter value should have
the same width as the port, and will be effectively XORed with it.

-inv <celltype> <portname_out>:<portname_in>

Specifies the cell type to use for the inverters and its port names.
This option is required.

Note

Help text automatically generated from passes/techmap/extractinv.cc:37

flowmap - pack LUTs with FlowMap¶

yosys> help flowmap¶

flowmap [options] [selection]¶

This pass uses the FlowMap technology mapping algorithm to pack logic gates
into k-LUTs with optimal depth. It allows mapping any circuit elements that can
be evaluated with the `eval` pass, including cells with multiple output ports
and multi-bit input and output ports.

-maxlut k

perform technology mapping for a k-LUT architecture. if not specified,
defaults to 3.

-minlut n

only produce n-input or larger LUTs. if not specified, defaults to 1.

-cells <cell>[,<cell>,...]

map specified cells. if not specified, maps $_NOT_, $_AND_, $_OR_,
$_XOR_ and $_MUX_, which are the outputs of the `simplemap` pass.

-relax

perform depth relaxation and area minimization.

-r-alpha n, -r-beta n, -r-gamma n

parameters of depth relaxation heuristic potential function.
if not specified, alpha=8, beta=2, gamma=1.

-optarea n

optimize for area by trading off at most n logic levels for fewer LUTs.
n may be zero, to optimize for area without increasing depth.
implies -relax.

-debug

dump intermediate graphs.

-debug-relax

explain decisions performed during depth relaxation.

Note

Help text automatically generated from passes/techmap/flowmap.cc:1475

hilomap - technology mapping of constant hi- and/or lo-drivers¶

yosys> help hilomap¶

hilomap [options] [selection]¶

Map constants to 'tielo' and 'tiehi' driver cells.

-hicell <celltype> <portname>

Replace constant hi bits with this cell.

-locell <celltype> <portname>

Replace constant lo bits with this cell.

-singleton

Create only one hi/lo cell and connect all constant bits
to that cell. Per default a separate cell is created for
each constant bit.

Note

Help text automatically generated from passes/techmap/hilomap.cc:57

insbuf - insert buffer cells for connected wires¶

yosys> help insbuf¶

insbuf [options] [selection]¶

Insert buffer cells into the design for directly connected wires.

-buf <celltype> <in-portname> <out-portname>

Use the given cell type instead of $_BUF_. (Notice that the next
call to "clean" will remove all $_BUF_ in the design.)

-chain

Chain buffer cells

Note

Help text automatically generated from passes/techmap/insbuf.cc:27

iopadmap - technology mapping of i/o pads (or buffers)¶

yosys> help iopadmap¶

iopadmap [options] [selection]¶

Map module inputs/outputs to PAD cells from a library. This pass
can only map to very simple PAD cells. Use 'techmap' to further map
the resulting cells to more sophisticated PAD cells.

-inpad <celltype> <in_port>[:<ext_port>]

Map module input ports to the given cell type with the
given output port name. if a 2nd portname is given, the
signal is passed through the pad cell, using the 2nd
portname as the port facing the module port.

-outpad <celltype> <out_port>[:<ext_port>]

-inoutpad <celltype> <io_port>[:<ext_port>]

Similar to -inpad, but for output and inout ports.

-toutpad <celltype> <oe_port>:<out_port>[:<ext_port>]

Merges $_TBUF_ cells into the output pad cell. This takes precedence
over the other -outpad cell. The first portname is the enable input
of the tristate driver, which can be prefixed with `~` for negative
polarity enable.

-tinoutpad <celltype> <oe_port>:<in_port>:<out_port>[:<ext_port>]

Merges $_TBUF_ cells into the inout pad cell. This takes precedence
over the other -inoutpad cell. The first portname is the enable input
of the tristate driver and the 2nd portname is the internal output
buffering the external signal.  Like with `-toutpad`, the enable can
be marked as negative polarity by prefixing the name with `~`.

-ignore <celltype> <portname>[:<portname>]*

Skips mapping inputs/outputs that are already connected to given
ports of the given cell.  Can be used multiple times.  This is in
addition to the cells specified as mapping targets.

-widthparam <param_name>

Use the specified parameter name to set the port width.

-nameparam <param_name>

Use the specified parameter to set the port name.

-bits

create individual bit-wide buffers even for ports that
are wider. (the default behavior is to create word-wide
buffers using -widthparam to set the word size on the cell.)

Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.

Note

Help text automatically generated from passes/techmap/iopadmap.cc:36

libcache - control caching of technology library data parsed from liberty files¶

yosys> help libcache¶

libcache {-enable|-disable|-purge} { -all | [path]... }¶

Controls the default and per path caching of liberty file data.

-enable Enable caching.

-disable Disable caching.

-purge Reset cache setting and forget cached data.

This mode takes a list of paths as argument. If no paths are provided, this
command does nothing. The -all option can be used to change the default cache
setting for -enable/-disable or to reset and forget about all paths.

By default caching is disabled.

    libcache -list

Displays the current cache settings and cached paths.

    libcache {-verbose|-quiet}

Controls cache use logging.

-verbose Enable printing info when cache is used

-quiet Disable printing info when cache is used (default)

Note

Help text automatically generated from passes/techmap/libcache.cc:27

lut2mux - convert $lut to $_MUX_¶

yosys> help lut2mux¶

lut2mux [options] [selection]¶

This pass converts $lut cells to $_MUX_ gates.

Note

Help text automatically generated from passes/techmap/lut2mux.cc:58

maccmap - mapping macc cells¶

yosys> help maccmap¶

maccmap [-unmap] [selection]¶

This pass maps $macc cells to yosys $fa and $alu cells. When the -unmap option
is used then the $macc cell is mapped to $add, $sub, etc. cells instead.

Note

Help text automatically generated from passes/techmap/maccmap.cc:377

muxcover - cover trees of MUX cells with wider MUXes¶

yosys> help muxcover¶

muxcover [options] [selection]¶

Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells

-mux4[=cost], -mux8[=cost], -mux16[=cost]

Cover $_MUX_ trees using the specified types of MUXes (with optional
integer costs). If none of these options are given, the effect is the
same as if all of them are.
Default costs: $_MUX4_ = 220, $_MUX8_ = 460,
$_MUX16_ = 940

-mux2=cost

Use the specified cost for $_MUX_ cells when making covering decisions.
Default cost: $_MUX_ = 100

-dmux=cost

Use the specified cost for $_MUX_ cells used in decoders.
Default cost: 90

-nodecode

Do not insert decoder logic. This reduces the number of possible
substitutions, but guarantees that the resulting circuit is not
less efficient than the original circuit.

-nopartial

Do not consider mappings that use $_MUX<N>_ to select from less
than <N> different signals.

Note

Help text automatically generated from passes/techmap/muxcover.cc:622

nlutmap - map to LUTs of different sizes¶

yosys> help nlutmap¶

nlutmap [options] [selection]¶

This pass uses successive calls to 'abc' to map to an architecture. That
provides a small number of differently sized LUTs.

-luts N_1,N_2,N_3,...

The number of LUTs with 1, 2, 3, ... inputs that are
available in the target architecture.

-assert

Create an error if not all logic can be mapped

Excess logic that does not fit into the specified LUTs is mapped back
to generic logic gates ($_AND_, etc.).

Note

Help text automatically generated from passes/techmap/nlutmap.cc:131

paramap - renaming cell parameters¶

yosys> help paramap¶

paramap [options] [selection]¶

This command renames cell parameters and/or maps key/value pairs to
other key/value pairs.

-tocase <name>

Match attribute names case-insensitively and set it to the specified
name.

-rename <old_name> <new_name>

Rename attributes as specified

-map <old_name>=<old_value> <new_name>=<new_value>

Map key/value pairs as indicated.

-imap <old_name>=<old_value> <new_name>=<new_value>

Like -map, but use case-insensitive match for <old_value> when
it is a string value.

-remove <name>=<value>

Remove attributes matching this pattern.

For example, mapping Diamond-style ECP5 "init" attributes to Yosys-style:

    paramap -tocase INIT t:LUT4

Note

Help text automatically generated from passes/techmap/attrmap.cc:297

pmuxtree - transform $pmux cells to trees of $mux cells¶

yosys> help pmuxtree¶

pmuxtree [selection]¶

This pass transforms $pmux cells to trees of $mux cells.

Note

Help text automatically generated from passes/techmap/pmuxtree.cc:69

shregmap - map shift registers¶

yosys> help shregmap¶

shregmap [options] [selection]¶

This pass converts chains of $_DFF_[NP]_ gates to target specific shift register
primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and
will use the same interface as the original $_DFF_*_ cells. The cell parameter
'DEPTH' will contain the depth of the shift register. Use a target-specific
'techmap' map file to convert those cells to the actual target cells.

-minlen N

minimum length of shift register (default = 2)
(this is the length after -keep_before and -keep_after)

-maxlen N

maximum length of shift register (default = no limit)
larger chains will be mapped to multiple shift register instances

-keep_before N

number of DFFs to keep before the shift register (default = 0)

-keep_after N

number of DFFs to keep after the shift register (default = 0)

-clkpol pos|neg|any

limit match to only positive or negative edge clocks. (default = any)

-enpol pos|neg|none|any_or_none|any

limit match to FFs with the specified enable polarity. (default = none)

-match <cell_type>[:<d_port_name>:<q_port_name>]

match the specified cells instead of $_DFF_N_ and $_DFF_P_. If
':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used
by default. E.g. the option '-clkpol pos' is just an alias for
'-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.

-params

instead of encoding the clock and enable polarity in the cell name by
deriving from the original cell name, simply name all generated cells
$__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is
used to denote cells without enable input. The ENPOL parameter is
omitted when '-enpol none' (or no -enpol option) is passed.

-zinit

assume the shift register is automatically zero-initialized, so it
becomes legal to merge zero initialized FFs into the shift register.

-init

map initialized registers to the shift reg, add an INIT parameter to
generated cells with the initialization value. (first bit to shift out
in LSB position)

-tech greenpak4

map to greenpak4 shift registers.

Note

Help text automatically generated from passes/techmap/shregmap.cc:376

simplemap - mapping simple coarse-grain cells¶

yosys> help simplemap¶

simplemap [selection]¶

This pass maps a small selection of simple coarse-grain cells to yosys gate
primitives. The following internal cell types are mapped by this pass:

  $not, $pos, $and, $or, $xor, $xnor
  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
  $logic_not, $logic_and, $logic_or, $mux, $tribuf
  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,
  $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr

Note

Help text automatically generated from passes/techmap/simplemap.cc:483

techmap - generic technology mapper¶

yosys> help techmap¶

techmap [-map filename] [selection]¶

This pass implements a very simple technology mapper that replaces cells in
the design with implementations given in form of a Verilog or RTLIL source
file.

-map filename

the library of cell implementations to be used.
without this parameter a builtin library is used that
transforms the internal RTL cells to the internal gate
library.

-map %<design-name>

like -map above, but with an in-memory design instead of a file.

-extern

load the cell implementations as separate modules into the design
instead of inlining them.

-max_iter <number>

only run the specified number of iterations on each module.
default: unlimited

-recursive

instead of the iterative breadth-first algorithm use a recursive
depth-first algorithm. both methods should yield equivalent results,
but may differ in performance.

-autoproc

Automatically call "proc" on implementations that contain processes.

-wb

Ignore the 'whitebox' attribute on cell implementations.

-assert

this option will cause techmap to exit with an error if it can't map
a selected cell. only cell types that end on an underscore are accepted
as final cell types by this mode.

-D <define>, -I <incdir>

this options are passed as-is to the Verilog frontend for loading the
map file. Note that the Verilog frontend is also called with the
'-nooverwrite' option set.

-dont_map <celltype>

leave the given cell type unmapped by ignoring any mapping rules for it

When a module in the map file has the 'techmap_celltype' attribute set, it will
match cells with a type that match the text value of this attribute. Otherwise
the module name will be used to match the cell.  Multiple space-separated cell
types can be listed, and wildcards using [] will be expanded (ie.
"$_DFF_[PN]_" is the same as "$_DFF_P_ $_DFF_N_").

When a module in the map file has the 'techmap_simplemap' attribute set, techmap
will use 'simplemap' (see 'help simplemap') to map cells matching the module.

When a module in the map file has the 'techmap_maccmap' attribute set, techmap
will use 'maccmap' (see 'help maccmap') to map cells matching the module.

When a module in the map file has the 'techmap_wrap' attribute set, techmap
will create a wrapper for the cell and then run the command string that the
attribute is set to on the wrapper module.

When a port on a module in the map file has the 'techmap_autopurge' attribute
set, and that port is not connected in the instantiation that is mapped, then
a cell port connected only to such wires will be omitted in the mapped version
of the circuit.

All wires in the modules from the map file matching the pattern _TECHMAP_*
or *._TECHMAP_* are special wires that are used to pass instructions from
the mapping module to the techmap command. At the moment the following special
wires are supported:

    _TECHMAP_FAIL_
        When this wire is set to a non-zero constant value, techmap will not
        use this module and instead try the next module with a matching
        'techmap_celltype' attribute.

        When such a wire exists but does not have a constant value after all
        _TECHMAP_DO_* commands have been executed, an error is generated.

    _TECHMAP_DO_*
        This wires are evaluated in alphabetical order. The constant text value
        of this wire is a yosys command (or sequence of commands) that is run
        by techmap on the module. A common use case is to run 'proc' on modules
        that are written using always-statements.

        When such a wire has a non-constant value at the time it is to be
        evaluated, an error is produced. That means it is possible for such a
        wire to start out as non-constant and evaluate to a constant value
        during processing of other _TECHMAP_DO_* commands.

        A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
        in this case techmap will create a copy for each distinct configuration
        of constant inputs and shorted inputs at this point and import the
        constant and connected bits into the map module. All further commands
        are executed in this copy. This is a very convenient way of creating
        optimized specializations of techmap modules without using the special
        parameters described below.

        A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
        then techmap will recursively replace the cells in the module with their
        implementation. This is not affected by the -max_iter option.

        It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.

    _TECHMAP_REMOVEINIT_<port-name>_
        When this wire is set to a constant value, the init attribute of the
        wire(s) connected to this port will be consumed.  This wire must have
        the same width as the given port, and for every bit that is set to 1 in
        the value, the corresponding init attribute bit will be changed to 1'bx.
        If all bits of an init attribute are left as x, it will be removed.

In addition to this special wires, techmap also supports special parameters in
modules in the map file:

    _TECHMAP_CELLTYPE_
        When a parameter with this name exists, it will be set to the type name
        of the cell that matches the module.

    _TECHMAP_CELLNAME_
        When a parameter with this name exists, it will be set to the name
        of the cell that matches the module.

    _TECHMAP_CONSTMSK_<port-name>_
    _TECHMAP_CONSTVAL_<port-name>_
        When this pair of parameters is available in a module for a port, then
        former has a 1-bit for each constant input bit and the latter has the
        value for this bit. The unused bits of the latter are set to undef (x).

    _TECHMAP_WIREINIT_<port-name>_
        When a parameter with this name exists, it will be set to the initial
        value of the wire(s) connected to the given port, as specified by the
        init attribute. If the attribute doesn't exist, x will be filled for the
        missing bits.  To remove the init attribute bits used, use the
        _TECHMAP_REMOVEINIT_*_ wires.

    _TECHMAP_BITS_CONNMAP_
    _TECHMAP_CONNMAP_<port-name>_
        For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
        exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
        N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
        bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
        This can be used to detect shorted inputs.

When a module in the map file has a parameter where the according cell in the
design has a port, the module from the map file is only used if the port in
the design is connected to a constant value. The parameter is then set to the
constant value.

A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
and attributes of the cell that is being replaced.
A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will
be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name
of the cell being replaced.
Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a
new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'
prefix also substituted.

A cell with the type _TECHMAP_PLACEHOLDER_ in the map file will have its type
changed to the content of the techmap_chtype attribute. This allows for choosing
the cell type dynamically.

See 'help extract' for a pass that does the opposite thing.

See 'help flatten' for a pass that does flatten the design (which is
essentially techmap but using the design itself as map library).

Note

Help text automatically generated from passes/techmap/techmap.cc:982

tribuf - infer tri-state buffers¶

yosys> help tribuf¶

tribuf [options] [selection]¶

This pass transforms $mux cells with 'z' inputs to tristate buffers.

-merge

merge multiple tri-state buffers driving the same net
into a single buffer.

-logic

convert tri-state buffers that do not drive output ports
to non-tristate logic. this option implies -merge.

-formal

convert all tri-state buffers to non-tristate logic and
add a formal assertion that no two buffers are driving the
same net simultaneously. this option implies -merge.

Note

Help text automatically generated from passes/techmap/tribuf.cc:179

zinit - add inverters so all FF are zero-initialized¶

yosys> help zinit¶

zinit [options] [selection]¶

Add inverters as needed to make all FFs zero-initialized.

-all

also add zero initialization to uninitialized FFs

Note

Help text automatically generated from passes/techmap/zinit.cc:29