More scripting

• Loading a design
  • Input files on the command line
  • The read command
  • Yosys frontends
    • The read_verilog command
    • Other built-in read_* commands
  • Externally maintained plugins
• Selections
  • The selection framework
  • How to make a selection
    • Selection by object name
    • Module and design context
    • Selecting by object property or type
  • Operations on selections
    • Combining selections
    • Expanding selections
    • Selecting logic cones
    • Advanced logic cone selection
    • Incremental selection
  • Storing and recalling selections
• Interactive design investigation
  • A look at the show command
    • A simple circuit
    • Break-out boxes for signal vectors
    • Gate level netlists
    • Miscellaneous notes
  • Navigating the design
    • Interactive navigation
  • Design Investigation
    • Changing design hierarchy
    • Behavioral changes
  • Advanced investigation techniques
    • Evaluation of combinatorial circuits
    • Solving combinatorial SAT problems
    • Solving sequential SAT problems
• Symbolic model checking
  • Checking techmap
  • AXI4 Stream Master
• Dataflow tracking
  • Example use cases
  • Semantics of dataflow tracking cells
  • Tag groups