Working with hierarchy¶

flatten - flatten design¶

yosys> help flatten¶

flatten [options] [selection]¶

This pass flattens the design by replacing cells by their implementation. This
pass is very similar to the 'techmap' pass. The only difference is that this
pass is using the current design as mapping library.

Cells and/or modules with the 'keep_hierarchy' attribute set will not be
flattened by this command.

-wb

Ignore the 'whitebox' attribute on cell implementations.

-noscopeinfo

Do not create '$scopeinfo' cells that preserve attributes of cells and
modules that were removed during flattening. With this option, the
'src' attribute of a given cell is merged into all objects replacing
that cell, with multiple distinct 'src' locations separated by '|'.
Without this option these 'src' locations can be found via the
cell_src' and 'module_src' attribute of '$scopeinfo' cells.

-scopename

Create 'scopename' attributes for objects with a private name. This
attribute records the 'hdlname' of the enclosing scope. For objects
with a public name the enclosing scope can be found via their
'hdlname' attribute.

-separator <char>

Use this separator char instead of '.' when concatenating design levels.

-nocleanup

Don't remove unused submodules, leave a flattened version of each
submodule in the design.

Note

Help text automatically generated from passes/hierarchy/flatten.cc:334

hierarchy - check, expand and clean up design hierarchy¶

yosys> help hierarchy¶

hierarchy [-check] [-top <module>]¶

hierarchy -generate <cell-types> <port-decls>¶

In parametric designs, a module might exists in several variations with
different parameter values. This pass looks at all modules in the current
design and re-runs the language frontends for the parametric modules as
needed. It also resolves assignments to wired logic data types (wand/wor),
resolves positional module parameters, unrolls array instances, and more.

-check

also check the design hierarchy. this generates an error when
an unknown module is used as cell type.

-simcheck

like -check, but also throw an error if blackbox modules are
instantiated, and throw an error if the design has no top module.

-smtcheck

like -simcheck, but allow smtlib2_module modules.

-purge_lib

by default the hierarchy command will not remove library (blackbox)
modules. use this option to also remove unused blackbox modules.

-libdir <directory>

search for files named <module_name>.v in the specified directory
for unknown modules and automatically run read_verilog for each
unknown module.

-keep_positionals

per default this pass also converts positional arguments in cells
to arguments using port names. This option disables this behavior.

-keep_portwidths

per default this pass adjusts the port width on cells that are
module instances when the width does not match the module port. This
option disables this behavior.

-nodefaults

do not resolve input port default values

-nokeep_prints

per default this pass sets the "keep" attribute on all modules
that directly or indirectly display text on the terminal.
This option disables this behavior.

-nokeep_asserts

per default this pass sets the "keep" attribute on all modules
that directly or indirectly contain one or more formal properties.
This option disables this behavior.

-top <module>

use the specified top module to build the design hierarchy. Modules
outside this tree (unused modules) are removed.

when the -top option is used, the 'top' attribute will be set on the
specified top module. otherwise a module with the 'top' attribute set
will implicitly be used as top module, if such a module exists.

-auto-top

automatically determine the top of the design hierarchy and mark it.

-chparam name value

elaborate the top module using this parameter value. Modules on which
this parameter does not exist may cause a warning message to be output.
This option can be specified multiple times to override multiple
parameters. String values must be passed in double quotes (").

In -generate mode this pass generates blackbox modules for the given cell
types (wildcards supported). For this the design is searched for cells that
match the given types and then the given port declarations are used to
determine the direction of the ports. The syntax for a port declaration is:

    {i|o|io}[@<num>]:<portname>

Input ports are specified with the 'i' prefix, output ports with the 'o'
prefix and inout ports with the 'io' prefix. The optional <num> specifies
the position of the port in the parameter list (needed when instantiated
using positional arguments). When <num> is not specified, the <portname> can
also contain wildcard characters.

This pass ignores the current selection and always operates on all modules
in the current design.

Note

Help text automatically generated from passes/hierarchy/hierarchy.cc:730

keep_hierarchy - selectively add the keep_hierarchy attribute¶

yosys> help keep_hierarchy¶

keep_hierarchy [options] [selection]¶

Add the keep_hierarchy attribute.

-min_cost <min_cost>

only add the attribute to modules estimated to have more than <min_cost>
gates after simple techmapping. Intended for tuning trade-offs between
quality and yosys runtime.

When evaluating a module's cost, gates which are within a submodule
which is marked with the keep_hierarchy attribute are not counted
towards the upper module's cost. This applies to both when the attribute
was added by this command or was pre-existing.

Note

Help text automatically generated from passes/hierarchy/keep_hierarchy.cc:82

submod - moving part of a module to a new submodule¶

yosys> help submod¶

submod [options] [selection]¶

This pass identifies all cells with the 'submod' attribute and moves them to
a newly created module. The value of the attribute is used as name for the
cell that replaces the group of cells with the same attribute value.

This pass can be used to create a design hierarchy in flat design. This can
be useful for analyzing or reverse-engineering a design.

This pass only operates on completely selected modules with no processes
or memories.

-copy

by default the cells are 'moved' from the source module and the source
module will use an instance of the new module after this command is
finished. call with -copy to not modify the source module.

-name <name>

don't use the 'submod' attribute but instead use the selection. only
objects from one module might be selected. the value of the -name option
is used as the value of the 'submod' attribute instead.

-hidden

instead of creating submodule ports with public names, create ports with
private names so that a subsequent 'flatten; clean' call will restore
the original module with original public names.

Note

Help text automatically generated from passes/hierarchy/submod.cc:322

uniquify - create unique copies of modules¶

yosys> help uniquify¶

uniquify [selection]¶

By default, a module that is instantiated by several other modules is only
kept once in the design. This preserves the original modularity of the design
and reduces the overall size of the design in memory. But it prevents certain
optimizations and other operations on the design. This pass creates unique
modules for all selected cells. The created modules are marked with the
'unique' attribute.

This commands only operates on modules that by themself have the 'unique'
attribute set (the 'top' module is unique implicitly).

Note

Help text automatically generated from passes/hierarchy/uniquify.cc:26