Microchip¶

microchip_dffopt - MICROCHIP: optimize FF control signal usage¶

yosys> help microchip_dffopt¶

microchip_dffopt [options] [selection]¶

Converts hardware clock enable and set/reset signals on FFs to emulation
using LUTs, if doing so would improve area. Operates on post-techmap LUT, DFF
cells. 

Note

Help text automatically generated from techlibs/microchip/microchip_dffopt.cc:102

microchip_dsp - MICROCHIP: pack resources into DSPs¶

yosys> help microchip_dsp¶

microchip_dsp [options] [selection]¶

Pack input registers 'A', 'B', 'C', and 'D' (with optional enable/reset),
output register 'P' (with optional enable/reset), pre-adder and/or post-adder into
Microchip DSP resources.

Multiply-accumulate operations using the post-adder with feedback on the 'C'
input will be folded into the DSP. In this scenario only, the 'C' input can be
used to override the current accumulation result with a new value. This will
be added to the multiplier result to form the next accumulation result.

Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'
connections (optionally, where 'P' is right-shifted by 17-bits and used as an
input to the post-adder. This pattern is common for summing partial products to
implement wide multipliers). Cascade chains are limited to a mazimum length 
of 24 cells, corresponding to PolarFire (pf) devices.

This pass is a no-op if the scratchpad variable 'microchip_dsp.multonly' is set
to 1.

-family {polarfire}

select the family to target
default: polarfire

Note

Help text automatically generated from techlibs/microchip/microchip_dsp.cc:275

synth_microchip - synthesis for Microchip FPGAs¶

yosys> help synth_microchip¶

synth_microchip [options]¶

This command runs synthesis for Microchip FPGAs. This command creates
netlists that are compatible with Microchip PolarFire devices. 

-top <module>

use the specified module as the top module

-family <family>

Run synthesis for the specified Microchip architecture.
Generate the synthesis netlist for the specified family.
supported values:
- polarfire: PolarFire

-edif <file>

Write the design to the specified edif file. Writing of an output file
is omitted if this parameter is not specified.

-blif <file>

Write the design to the specified BLIF file. Writing of an output file
is omitted if this parameter is not specified.

-vlog <file>

write the design to the specified Verilog file. writing of an output
file is omitted if this parameter is not specified.

-nobram

Do not use block RAM cells in output netlist

-nocarry

Do not use ARI1 cells in output netlist

-nodsp

Do not use MATH blocks to implement multipliers and associated logic

-noiopad

Disable I/O buffer insertion (useful for hierarchical or
out-of-context flows)

-noclkbuf

Disable automatic clock buffer insertion

-run <from_label>:<to_label>

Only run the commands between the labels (see below). an empty
'from_label' is synonymous to 'begin', and empty 'to_label' is
synonymous to the end of the command list.

-noflatten

do not flatten design before synthesis

-dff

Run 'abc'/'abc9' with -dff option

-retime

Run 'abc' with '-D 1' option to enable flip-flop retiming.
implies -dff.

-noabc9

Use classic ABC flow instead of ABC9

-discard-ffinit

discard FF init value instead of emitting an error

The following commands are executed by this synthesis command:

begin:
    read_verilog -lib -specify +/microchip/cells_sim.v
    hierarchy -check -auto-top

prepare:
    proc
    flatten    (with '-flatten')
    tribuf -logic
    deminout
    opt_expr
    opt_clean
    check
    opt -nodffe -nosdff
    fsm
    opt
    wreduce
    peepopt
    opt_clean

map_dsp:    (skip if '-nodsp')
    memory_dff
    techmap -map +/mul2dsp.v -map +/microchip/{family}_dsp_map.v {options}
    select a:mul2dsp
    setattr -unset mul2dsp
    opt_expr -fine
    wreduce
    select -clear
    microchip_dsp -family <family>
    chtype -set $mul t:$__soft_mul

coarse:
    techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=[4]
    alumacc
    share
    opt
    memory -nomap
    opt_clean
    attrmap -remove init    (only if -discard-ffinit)

map_memory:
    memory_libmap [...]
    techmap -map +/microchip/LSRAM_map.v
    techmap -map +/microchip/uSRAM_map.v

map_ffram:
    opt -fast -full
    memory_map

fine:
    opt -full
    simplemap t:$mux
    simplemap t:$xor
    extract_reduce
    muxcover -nodecode -mux4=220
    techmap -map +/microchip/arith_map.v
    techmap -map +/techmap.v
    opt -fast

map_cells:
    iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD    (unless -noiobs)
    techmap -map +/techmap.v -map +/microchip/cells_map.v
    clean

map_ffs:
    dfflegalize -cell $_DFFE_PN?P_ x -cell $_SDFFCE_PN?P_ x -cell $_DLATCH_PN?_ x    (Converts FFs to supported types)
    zinit -all w:* t:$_SDFFCE_*    ('-dff' only)
    techmap -D NO_LUT -map +/microchip/cells_map.v    ('-abc9' only)

map_luts:
    opt_expr -mux_undef -noclkinv
    abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]    (option for '-nowidelut', '-dff', '-retime')
    clean
    techmap -D NO_LUT -map +/microchip/cells_map.v    (only if not '-abc9')
    techmap -map +/microchip/cells_map.v -D FINAL_MAP -D LUT_WIDTH=[4]
    microchip_dffopt
    clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD
    clean -purge

check:
    hierarchy -check
    stat
    check -noinit
    blackbox =A:whitebox

edif:
    write_edif -pvector bra 

blif:
    write_blif 

vlog:
    write_verilog <file-name>

Note

Help text automatically generated from techlibs/microchip/synth_microchip.cc:28