Loading a design

Input files on the command line

• guesses frontend based on file extension

  • .v -> read -vlog2k

  • .sv -> read -sv

  • .vhd and .vhdl -> read -vhdl

  • .blif and .eblif -> read_blif

  • .json -> read_json

  • .il -> read_rtlil (direct textual representation of Yosys internal state)

• command line also supports

  • .ys -> script

  • .tcl -> tcl

  • - -> reads stdin and treats it as a script

The read command

• standard method of loading designs

• also for defining macros and include directories

• uses verific command if available

  • -verific and -noverific options to enforce with/without Verific

  • check help read for more about the options available and the filetypes supported

  • elaborate designs with verific -import [options] <top> (or use hierarchy)

• fallback to read_verilog with -defer option

  • does not compile design until hierarchy command as discussed in Synthesis starter

  • more similar to verific behaviour

• read -define et al mapped to verific or verilog_defines

• similarly, read -incdir et al mapped to verific or verilog_defaults

Note

The Verific frontend for Yosys, which provides the verific command, requires Yosys to be built with Verific. For full functionality, custom modifications to the Verific source code from YosysHQ are required, but limited useability can be achieved with some stock Verific builds. Check Compiling with Verific library for more.

Yosys frontends

• Reading input files

• typically start with read_

• built-in support for heredocs

  • in-line code with <<EOT

  • can use any eot marker, but EOT (End-of-Transmission) and EOF (End-of-File) are most common

• built-in support for reading multiple files in the same command

  • executed as multiple successive calls to the frontend

• compatible with -f command line option, e.g. yosys -f verilog design.txt will use the read_verilog frontend with the input file design.txt

• verific and read commands are technically not ‘Frontends’, but their behaviour is kept in sync

Note

‘Frontend’ here means that the command is implemented as a sub-class of RTLIL::Frontend, as opposed to the usual RTLIL::Pass.

The read_verilog command

• read_verilog - read modules from Verilog file; also

  • verilog_defaults - set default options for read_verilog,

  • verilog_defines - define and undefine verilog defines, and

  • read_verilog_file_list - parse a Verilog file list

• supports most of Verilog-2005

• limited support for SystemVerilog

• some non-standard features/extensions for enabling formal verification

• please do not rely on read_verilog for syntax checking

  • recommend using a simulator (for example Icarus Verilog) or linting with another tool (such as verilator) first

read_verilog file1.v
read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
read_verilog -lib cell_library.v

verilog_defaults -add -I include_dir
read_verilog file3.v
read_verilog file4.v
verilog_defaults -clear

verilog_defaults -push
verilog_defaults -add -I include_dir
read_verilog file5.v
read_verilog file6.v
verilog_defaults -pop

Other built-in read_* commands

• read_rtlil - read modules from RTLIL file

• read_aiger - read AIGER file

• read_blif - read BLIF file

• read_json - read JSON file

• read_liberty - read cells from liberty file

• read_xaiger2 - (experimental) read XAIGER file

Externally maintained plugins

• GHDL plugin for VHDL (check help ghdl)

• yosys-slang plugin for more comprehensive SystemVerilog support (check help read_slang)

  • yosys-slang is implemented as a ‘Frontend,’ with all the built-in support that entails

• both plugins above are included in OSS CAD Suite

• Synlig, which uses Surelog to provide SystemVerilog support

  • also implemented as a ‘Frontend’