Xilinx¶

synth_xilinx - synthesis for Xilinx FPGAs¶

yosys> help synth_xilinx¶

synth_xilinx [options]¶

This command runs synthesis for Xilinx FPGAs. This command does not operate on
partly selected designs. At the moment this command creates netlists that are
compatible with 7-Series Xilinx devices.

-top <module>

use the specified module as top module

-family <family>

run synthesis for the specified Xilinx architecture
generate the synthesis netlist for the specified family.
supported values:
- xcup: Ultrascale Plus
- xcu: Ultrascale
- xc7: Series 7 (default)
- xc6s: Spartan 6
- xc6v: Virtex 6
- xc5v: Virtex 5 (EXPERIMENTAL)
- xc4v: Virtex 4 (EXPERIMENTAL)
- xc3sda: Spartan 3A DSP (EXPERIMENTAL)
- xc3sa: Spartan 3A (EXPERIMENTAL)
- xc3se: Spartan 3E (EXPERIMENTAL)
- xc3s: Spartan 3 (EXPERIMENTAL)
- xc2vp: Virtex 2 Pro (EXPERIMENTAL)
- xc2v: Virtex 2 (EXPERIMENTAL)
- xcve: Virtex E, Spartan 2E (EXPERIMENTAL)
- xcv: Virtex, Spartan 2 (EXPERIMENTAL)

-edif <file>

write the design to the specified edif file. writing of an output file
is omitted if this parameter is not specified.

-blif <file>

write the design to the specified BLIF file. writing of an output file
is omitted if this parameter is not specified.

-ise

generate an output netlist suitable for ISE

-nobram

do not use block RAM cells in output netlist

-nolutram

do not use distributed RAM cells in output netlist

-nosrl

do not use distributed SRL cells in output netlist

-nocarry

do not use XORCY/MUXCY/CARRY4 cells in output netlist

-nowidelut

do not use MUXF[5-9] resources to implement LUTs larger than native for
the target

-nodsp

do not use DSP48*s to implement multipliers and associated logic

-noiopad

disable I/O buffer insertion (useful for hierarchical or
out-of-context flows)

-noclkbuf

disable automatic clock buffer insertion

-uram

infer URAM288s for large memories (xcup only)

-widemux <int>

enable inference of hard multiplexer resources (MUXF[78]) for muxes at
or above this number of inputs (minimum value 2, recommended value >= 5)
default: 0 (no inference)

-json <file>

write the design to the specified JSON file. writing of an output file
is omitted if this parameter is not specified.

-run <from_label>:<to_label>

only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.

-flatten

flatten design before synthesis

-dff

run 'abc'/'abc9' with -dff option

-retime

run 'abc' with '-D 1' option to enable flip-flop retiming.
implies -dff.

-abc9

use new ABC9 flow (EXPERIMENTAL)

The following commands are executed by this synthesis command:

begin:
    read_verilog -lib -specify +/xilinx/cells_sim.v
    read_verilog -lib +/xilinx/cells_xtra.v
    hierarchy -check -auto-top

prepare:
    proc
    flatten    (with '-flatten')
    tribuf -logic
    deminout
    opt_expr
    opt_clean
    check
    opt -nodffe -nosdff
    fsm
    opt
    wreduce [-keepdc]    (option for '-widemux')
    peepopt
    opt_clean
    muxpack        ('-widemux' only)
    pmux2shiftx    (skip if '-nosrl' and '-widemux=0')
    clean          (skip if '-nosrl' and '-widemux=0')

map_dsp:    (skip if '-nodsp')
    memory_dff
    techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}
    select a:mul2dsp
    setattr -unset mul2dsp
    opt_expr -fine
    wreduce
    select -clear
    xilinx_dsp -family <family>
    chtype -set $mul t:$__soft_mul

coarse:
    techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=[46]
    alumacc
    share
    opt
    memory -nomap
    opt_clean

map_memory:
    memory_libmap [...]
    techmap -map +/xilinx/lutrams_<family>_map.v
    techmap -map +/xilinx/brams_<family>_map.v

map_ffram:
    opt -fast -full
    memory_map

fine:
    simplemap t:$mux    ('-widemux' only)
    muxcover <internal options>    ('-widemux' only)
    opt -full
    xilinx_srl -variable -minlen 3    (skip if '-nosrl')
    techmap  -map +/techmap.v -D LUT_SIZE=[46] [-map +/xilinx/mux_map.v] -map +/xilinx/arith_map.v
    opt -fast

map_cells:
    iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top    (skip if '-noiopad')
    techmap -map +/techmap.v -map +/xilinx/cells_map.v
    clean

map_ffs:
    dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01    (for xc6v, xc7, xcu, xcup)
    zinit -all w:* t:$_SDFFE_*    ('-dff' only)
    techmap -map +/xilinx/ff_map.v    ('-abc9' only)

map_luts:
    opt_expr -mux_undef -noclkinv
    abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]    (option for '-nowidelut', '-dff', '-retime')
    clean
    techmap -map +/xilinx/ff_map.v    (only if not '-abc9')
    xilinx_srl -fixed -minlen 3    (skip if '-nosrl')
    techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -D LUT_WIDTH=[46]
    xilinx_dffopt [-lut4]
    opt_lut_ins -tech xilinx

finalize:
    clkbufmap -buf BUFG O:I    (skip if '-noclkbuf')
    extractinv -inv INV O:I    (only if '-ise')
    clean

check:
    hierarchy -check
    stat -tech xilinx
    check -noinit
    blackbox =A:whitebox

edif:
    write_edif -pvector bra 

blif:
    write_blif 

json:
    write_json <file-name>

Note

Help text automatically generated from techlibs/xilinx/synth_xilinx.cc:31

xilinx_dffopt - Xilinx: optimize FF control signal usage¶

yosys> help xilinx_dffopt¶

xilinx_dffopt [options] [selection]¶

Converts hardware clock enable and set/reset signals on FFs to emulation
using LUTs, if doing so would improve area.  Operates on post-techmap Xilinx
cells (LUT*, FD*).

-lut4

Assume a LUT4-based device (instead of a LUT6-based device).

Note

Help text automatically generated from techlibs/xilinx/xilinx_dffopt.cc:101

xilinx_dsp - Xilinx: pack resources into DSPs¶

yosys> help xilinx_dsp¶

xilinx_dsp [options] [selection]¶

Pack input registers (A2, A1, B2, B1, C, D, AD; with optional enable/reset),
pipeline registers (M; with optional enable/reset), output registers (P; with
optional enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.

Multiply-accumulate operations using the post-adder with feedback on the 'C'
input will be folded into the DSP. In this scenario only, the 'C' input can be
used to override the current accumulation result with a new value, which will
be added to the multiplier result to form the next accumulation result.

Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'
connections (optionally, where 'P' is right-shifted by 17-bits and used as an
input to the post-adder -- a pattern common for summing partial products to
implement wide multipliers). Limited support also exists for similar cascading
for A and B using '[AB]COUT' -> '[AB]CIN'. Currently, cascade chains are limited
to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series
device.

This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set
to 1.

Experimental feature: addition/subtractions less than 12 or 24 bits with the
'(* use_dsp="simd" *)' attribute attached to the output wire or attached to
the add/subtract operator will cause those operations to be implemented using
the 'SIMD' feature of DSPs.

Experimental feature: the presence of a `$ge' cell attached to the registered
P output implementing the operation "(P >= <power-of-2>)" will be transformed
into using the DSP48E1's pattern detector feature for overflow detection.

-family {xcup|xcu|xc7|xc6v|xc5v|xc4v|xc6s|xc3sda}

select the family to target
default: xc7

Note

Help text automatically generated from techlibs/xilinx/xilinx_dsp.cc:729

xilinx_srl - Xilinx shift register extraction¶

yosys> help xilinx_srl¶

xilinx_srl [options] [selection]¶

This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*
and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a
$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock
polarity, enable, and enable polarity (where relevant).
Flops with resets cannot be mapped to Xilinx devices and will not be inferred.

-minlen N

min length of shift register (default = 3)

-fixed

infer fixed-length shift registers.

-variable

infer variable-length shift registers (i.e. fixed-length shifts where
each element also fans-out to a $shiftx cell).

Note

Help text automatically generated from techlibs/xilinx/xilinx_srl.cc:190