Yosys Open SYnthesis Suite

Yosys is an open source framework for RTL synthesis. To learn more about Yosys, see What is Yosys. For a quick guide on how to get started using Yosys, check out Getting started with Yosys. For the complete list of commands available, go to Command Reference.

• Yosys (index)
• What is Yosys
  • What you can do with Yosys
    • Typical applications for Yosys
    • Things you can’t do
  • The Yosys family
  • The original thesis abstract
    • Benefits of open source HDL synthesis
    • History of Yosys
• Getting started with Yosys
  • Installation
    • CAD suite(s)
    • Building from source
    • Source tree and build system
  • Synthesis starter
    • Demo design
    • Loading the design
    • Elaboration
    • Flattening
    • The coarse-grain representation
    • Hardware mapping
    • Final steps
  • Scripting in Yosys
    • Script parsing
    • The synthesis starter script
• Using Yosys (advanced)
  • Synthesis in detail
    • Synth commands
    • Converting process blocks
    • FSM handling
    • Memory handling
    • Optimization passes
    • Technology mapping
    • The extract pass
    • The ABC toolbox
    • Mapping to cell libraries
  • More scripting
    • Loading a design
    • Selections
    • Interactive design investigation
    • Symbolic model checking
• Yosys internals
  • Internal flow
    • Flow overview
    • Control and data flow
    • The Verilog and AST frontends
  • Internal formats
    • The RTL Intermediate Language (RTLIL)
  • Working with the Yosys codebase
    • Writing extensions
    • Compiling with Verific library
    • Writing a new backend using FunctionalIR
    • Contributing to Yosys
    • Testing Yosys
  • Techmap by example
    • Mapping OR3X1
    • Conditional techmap
    • Scripting in map modules
    • Handling constant inputs
    • Handling shorted inputs
    • Notes on using techmap
  • Notes on Verilog support in Yosys
    • Unsupported Verilog-2005 Features
    • Verilog Attributes and non-standard features
    • Non-standard or SystemVerilog features for formal verification
    • Supported features from SystemVerilog
  • Hashing and associative data structures in Yosys
    • Container classes based on hashing
    • The hash function
    • Making a type hashable
    • Porting plugins from the legacy interface

Appendix

• A primer on digital circuit synthesis
• RTLIL text representation
• Auxiliary libraries
• Auxiliary programs
• Literature references
• Internal cell library
  • Word-level cells
    • Unary operators
    • Binary operators
    • Multiplexers
    • Registers
    • Memories
    • Finite state machines
    • Coarse arithmetics
    • Arbitrary logic functions
    • Specify rules
    • Formal verification cells
    • Debugging cells
    • Wire cells
  • Gate-level cells
    • Combinatorial cells (simple)
    • Combinatorial cells (combined)
    • Flip-flop cells
    • Latch cells
    • Other gate-level cells
  • Cell properties
• Command line reference
  • Yosys environment variables
  • abc - use ABC for technology mapping
  • abc9 - use ABC9 for technology mapping
  • abc9_exe - use ABC9 for technology mapping
  • abc9_ops - helper functions for ABC9
  • abc_new - (experimental) use ABC for SC technology mapping (new)
  • add - add objects to the design
  • aigmap - map logic to and-inverter-graph circuit
  • alumacc - extract ALU and MACC cells
  • anlogic_eqn - Anlogic: Calculate equations for luts
  • anlogic_fixcarry - Anlogic: fix carry chain
  • assertpmux - adds asserts for parallel muxes
  • async2sync - convert async FF inputs to sync circuits
  • attrmap - renaming attributes
  • attrmvcp - move or copy attributes from wires to driving cells
  • autoname - automatically assign names to objects
  • blackbox - convert modules into blackbox modules
  • bmuxmap - transform $bmux cells to trees of $mux cells
  • booth - map $mul cells to Booth multipliers
  • box_derive - derive box modules
  • bufnorm - (experimental) convert design into buffered-normalized form
  • bugpoint - minimize testcases
  • bwmuxmap - replace $bwmux cells with equivalent logic
  • cd - a shortcut for ‘select -module <name>’
  • cellmatch - match cells to their targets in cell library
  • check - check for obvious problems in the design
  • chformal - change formal constraints of the design
  • chparam - re-evaluate modules with new parameters
  • chtype - change type of cells in the design
  • clean - remove unused cells and wires
  • clean_zerowidth - clean zero-width connections from the design
  • clk2fflogic - convert clocked FFs to generic $ff cells
  • clkbufmap - insert clock buffers on clock networks
  • clockgate - extract clock gating out of flip flops
  • connect - create or remove connections
  • connect_rpc - connect to RPC frontend
  • connwrappers - match width of input-output port pairs
  • coolrunner2_fixup - insert necessary buffer cells for CoolRunner-II architecture
  • coolrunner2_sop - break $sop cells into ANDTERM/ORTERM cells
  • copy - copy modules in the design
  • cover - print code coverage counters
  • cutpoint - adds formal cut points to the design
  • debug - run command with debug log messages enabled
  • delete - delete objects in the design
  • deminout - demote inout ports to input or output
  • demuxmap - transform $demux cells to $eq + $mux cells
  • design - save, restore and reset current design
  • dffinit - set INIT param on FF cells
  • dfflegalize - convert FFs to types supported by the target
  • dfflibmap - technology mapping of flip-flops
  • dffunmap - unmap clock enable and synchronous reset from FFs
  • dft_tag - create tagging logic for data flow tracking
  • dump - print parts of the design in RTLIL format
  • echo - turning echoing back of commands on and off
  • edgetypes - list all types of edges in selection
  • efinix_fixcarry - Efinix: fix carry chain
  • equiv_add - add a $equiv cell
  • equiv_induct - proving $equiv cells using temporal induction
  • equiv_make - prepare a circuit for equivalence checking
  • equiv_mark - mark equivalence checking regions
  • equiv_miter - extract miter from equiv circuit
  • equiv_opt - prove equivalence for optimized circuit
  • equiv_purge - purge equivalence checking module
  • equiv_remove - remove $equiv cells
  • equiv_simple - try proving simple $equiv instances
  • equiv_status - print status of equivalent checking module
  • equiv_struct - structural equivalence checking
  • eval - evaluate the circuit given an input
  • example_dt - drivertools example
  • exec - execute commands in the operating system shell
  • expose - convert internal signals to module ports
  • extract - find subcircuits and replace them with cells
  • extract_counter - Extract GreenPak4 counter cells
  • extract_fa - find and extract full/half adders
  • extract_reduce - converts gate chains into $reduce_* cells
  • extractinv - extract explicit inverter cells for invertible cell pins
  • flatten - flatten design
  • flowmap - pack LUTs with FlowMap
  • fmcombine - combine two instances of a cell into one
  • fminit - set init values/sequences for formal
  • formalff - prepare FFs for formal
  • freduce - perform functional reduction
  • fsm - extract and optimize finite state machines
  • fsm_detect - finding FSMs in design
  • fsm_expand - expand FSM cells by merging logic into it
  • fsm_export - exporting FSMs to KISS2 files
  • fsm_extract - extracting FSMs in design
  • fsm_info - print information on finite state machines
  • fsm_map - mapping FSMs to basic logic
  • fsm_opt - optimize finite state machines
  • fsm_recode - recoding finite state machines
  • fst2tb - generate testbench out of fst file
  • future - resolve future sampled value functions
  • gatemate_foldinv - fold inverters into Gatemate LUT trees
  • glift - create GLIFT models and optimization problems
  • greenpak4_dffinv - merge greenpak4 inverters and DFF/latches
  • help - display help messages
  • hierarchy - check, expand and clean up design hierarchy
  • hilomap - technology mapping of constant hi- and/or lo-drivers
  • history - show last interactive commands
  • ice40_braminit - iCE40: perform SB_RAM40_4K initialization from file
  • ice40_dsp - iCE40: map multipliers
  • ice40_opt - iCE40: perform simple optimizations
  • ice40_wrapcarry - iCE40: wrap carries
  • insbuf - insert buffer cells for connected wires
  • internal_stats - print internal statistics
  • iopadmap - technology mapping of i/o pads (or buffers)
  • jny - write design and metadata
  • json - write design in JSON format
  • keep_hierarchy - selectively add the keep_hierarchy attribute
  • lattice_gsr - Lattice: handle GSR
  • license - print license terms
  • log - print text and log files
  • logger - set logger properties
  • ls - list modules or objects in modules
  • ltp - print longest topological path
  • lut2mux - convert $lut to $_MUX_
  • maccmap - mapping macc cells
  • memory - translate memories to basic cells
  • memory_bmux2rom - convert muxes to ROMs
  • memory_bram - map memories to block rams
  • memory_collect - creating multi-port memory cells
  • memory_dff - merge input/output DFFs into memory read ports
  • memory_libmap - map memories to cells
  • memory_map - translate multiport memories to basic cells
  • memory_memx - emulate vlog sim behavior for mem ports
  • memory_narrow - split up wide memory ports
  • memory_nordff - extract read port FFs from memories
  • memory_share - consolidate memory ports
  • memory_unpack - unpack multi-port memory cells
  • microchip_dffopt - MICROCHIP: optimize FF control signal usage
  • microchip_dsp - MICROCHIP: pack resources into DSPs
  • miter - automatically create a miter circuit
  • mutate - generate or apply design mutations
  • muxcover - cover trees of MUX cells with wider MUXes
  • muxpack - $mux/$pmux cascades to $pmux
  • nlutmap - map to LUTs of different sizes
  • nx_carry - NanoXplore: create carry cells
  • onehot - optimize $eq cells for onehot signals
  • opt - perform simple optimizations
  • opt_clean - remove unused cells and wires
  • opt_demorgan - Optimize reductions with DeMorgan equivalents
  • opt_dff - perform DFF optimizations
  • opt_expr - perform const folding and simple expression rewriting
  • opt_ffinv - push inverters through FFs
  • opt_lut - optimize LUT cells
  • opt_lut_ins - discard unused LUT inputs
  • opt_mem - optimize memories
  • opt_mem_feedback - convert memory read-to-write port feedback paths to write enables
  • opt_mem_priority - remove priority relations between write ports that can never collide
  • opt_mem_widen - optimize memories where all ports are wide
  • opt_merge - consolidate identical cells
  • opt_muxtree - eliminate dead trees in multiplexer trees
  • opt_reduce - simplify large MUXes and AND/OR gates
  • opt_share - merge mutually exclusive cells of the same type that share an input signal
  • paramap - renaming cell parameters
  • peepopt - collection of peephole optimizers
  • plugin - load and list loaded plugins
  • pmux2shiftx - transform $pmux cells to $shiftx cells
  • pmuxtree - transform $pmux cells to trees of $mux cells
  • portarcs - derive port arcs for propagation delay
  • portlist - list (top-level) ports
  • prep - generic synthesis script
  • printattrs - print attributes of selected objects
  • proc - translate processes to netlists
  • proc_arst - detect asynchronous resets
  • proc_clean - remove empty parts of processes
  • proc_dff - extract flip-flops from processes
  • proc_dlatch - extract latches from processes
  • proc_init - convert initial block to init attributes
  • proc_memwr - extract memory writes from processes
  • proc_mux - convert decision trees to multiplexers
  • proc_prune - remove redundant assignments
  • proc_rmdead - eliminate dead trees in decision trees
  • proc_rom - convert switches to ROMs
  • qbfsat - solve a 2QBF-SAT problem in the circuit
  • ql_bram_merge - Infers QuickLogic k6n10f BRAM pairs that can operate independently
  • ql_bram_types - Change TDP36K type to subtypes
  • ql_dsp_io_regs - change types of QL_DSP2 depending on configuration
  • ql_dsp_macc - infer QuickLogic multiplier-accumulator DSP cells
  • ql_dsp_simd - merge QuickLogic K6N10f DSP pairs to operate in SIMD mode
  • read - load HDL designs
  • read_aiger - read AIGER file
  • read_blif - read BLIF file
  • read_json - read JSON file
  • read_liberty - read cells from liberty file
  • read_rtlil - read modules from RTLIL file
  • read_verilog - read modules from Verilog file
  • read_xaiger2 - (experimental) read XAIGER file
  • recover_names - Execute a lossy mapping command and recover original netnames
  • rename - rename object in the design
  • rmports - remove module ports with no connections
  • sat - solve a SAT problem in the circuit
  • scatter - add additional intermediate nets
  • scc - detect strongly connected components (logic loops)
  • scratchpad - get/set values in the scratchpad
  • script - execute commands from file or wire
  • select - modify and view the list of selected objects
  • setattr - set/unset attributes on objects
  • setenv - set an environment variable
  • setparam - set/unset parameters on objects
  • setundef - replace undef values with defined constants
  • share - perform sat-based resource sharing
  • shell - enter interactive command mode
  • show - generate schematics using graphviz
  • shregmap - map shift registers
  • sim - simulate the circuit
  • simplemap - mapping simple coarse-grain cells
  • splice - create explicit splicing cells
  • splitcells - split up multi-bit cells
  • splitnets - split up multi-bit nets
  • sta - perform static timing analysis
  • stat - print some statistics
  • submod - moving part of a module to a new submodule
  • supercover - add hi/lo cover cells for each wire bit
  • synth - generic synthesis script
  • synth_achronix - synthesis for Achronix Speedster22i FPGAs.
  • synth_anlogic - synthesis for Anlogic FPGAs
  • synth_coolrunner2 - synthesis for Xilinx Coolrunner-II CPLDs
  • synth_easic - synthesis for eASIC platform
  • synth_ecp5 - synthesis for ECP5 FPGAs
  • synth_efinix - synthesis for Efinix FPGAs
  • synth_fabulous - FABulous synthesis script
  • synth_gatemate - synthesis for Cologne Chip GateMate FPGAs
  • synth_gowin - synthesis for Gowin FPGAs
  • synth_greenpak4 - synthesis for GreenPAK4 FPGAs
  • synth_ice40 - synthesis for iCE40 FPGAs
  • synth_intel - synthesis for Intel (Altera) FPGAs.
  • synth_intel_alm - synthesis for ALM-based Intel (Altera) FPGAs.
  • synth_lattice - synthesis for Lattice FPGAs
  • synth_microchip - synthesis for Microchip FPGAs
  • synth_nanoxplore - synthesis for NanoXplore FPGAs
  • synth_nexus - synthesis for Lattice Nexus FPGAs
  • synth_quicklogic - Synthesis for QuickLogic FPGAs
  • synth_sf2 - synthesis for SmartFusion2 and IGLOO2 FPGAs
  • synth_xilinx - synthesis for Xilinx FPGAs
  • synthprop - synthesize SVA properties
  • tcl - execute a TCL script file
  • techmap - generic technology mapper
  • tee - redirect command output to file
  • test_abcloop - automatically test handling of loops in abc command
  • test_autotb - generate simple test benches
  • test_cell - automatically test the implementation of a cell type
  • test_generic - test the generic compute graph
  • test_pmgen - test pass for pmgen
  • torder - print cells in topological order
  • trace - redirect command output to file
  • tribuf - infer tri-state buffers
  • uniquify - create unique copies of modules
  • verific - load Verilog and VHDL designs using Verific
  • verilog_defaults - set default options for read_verilog
  • verilog_defines - define and undefine verilog defines
  • viz - visualize data flow graph
  • wbflip - flip the whitebox attribute
  • wrapcell - wrap individual cells into new modules
  • wreduce - reduce the word size of operations if possible
  • write_aiger - write design to AIGER file
  • write_aiger2 - (experimental) write design to AIGER file
  • write_blif - write design to BLIF file
  • write_btor - write design to BTOR file
  • write_cxxrtl - convert design to C++ RTL simulation
  • write_edif - write design to EDIF netlist file
  • write_file - write a text to a file
  • write_firrtl - write design to a FIRRTL file
  • write_functional_cxx - convert design to C++ using the functional backend
  • write_functional_rosette - Generate Rosette compatible Racket from Functional IR
  • write_functional_smt2 - Generate SMT-LIB from Functional IR
  • write_intersynth - write design to InterSynth netlist file
  • write_jny - generate design metadata
  • write_json - write design to a JSON file
  • write_rtlil - write design to RTLIL file
  • write_simplec - convert design to simple C code
  • write_smt2 - write design to SMT-LIBv2 file
  • write_smv - write design to SMV file
  • write_spice - write design to SPICE netlist file
  • write_table - write design as connectivity table
  • write_verilog - write design to Verilog file
  • write_xaiger - write design to XAIGER file
  • write_xaiger2 - (experimental) write module to XAIGER file
  • xilinx_dffopt - Xilinx: optimize FF control signal usage
  • xilinx_dsp - Xilinx: pack resources into DSPs
  • xilinx_srl - Xilinx shift register extraction
  • xprop - formal x propagation
  • zinit - add inverters so all FF are zero-initialized