Synthesis in detail¶
Synthesis can generally be broken down into coarse-grain synthesis, and fine-grain synthesis. We saw this in Synthesis starter where a design was loaded and elaborated and then went through a series of coarse-grain optimizations before being mapped to hard blocks and fine-grain cells. Most commands in Yosys will target either coarse-grain representation or fine-grain representation, with only a select few compatible with both states.
Commands such as proc
, fsm
, and memory
rely on the additional information
in the coarse-grain representation, along with a number of optimizations such as
wreduce
, share
, and alumacc
. opt
provides optimizations which are
useful in both states, while techmap
is used to convert coarse-grain cells to
the corresponding fine-grain representation.
Single-bit cells (logic gates, FFs) as well as LUTs, half-adders, and
full-adders make up the bulk of the fine-grain representation and are necessary
for commands such as abc
/abc9
, simplemap
, dfflegalize
, and
memory_map
.
- Synth commands
- Converting process blocks
- FSM handling
- Memory handling
- Optimization passes
- The
opt
macro command- Constant folding and simple expression rewriting -
opt_expr
- Merging identical cells -
opt_merge
- Removing never-active branches from multiplexer tree -
opt_muxtree
- Simplifying large MUXes and AND/OR gates -
opt_reduce
- Merging mutually exclusive cells with shared inputs -
opt_share
- Performing DFF optimizations -
opt_dff
- Removing unused cells and wires -
opt_clean
pass - When to use
opt
orclean
- Constant folding and simple expression rewriting -
- Other optimizations
- The
- Technology mapping
- The extract pass
- The ABC toolbox
- Mapping to cell libraries