Most of today’s digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools.
In special cases such as synthesis for coarse-grain cell libraries or when testing new synthesis algorithms it might be necessary to write a custom HDL synthesis tool or add new features to an existing one. In these cases the availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful.
In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was developed. This document covers the design and implementation of this tool. At the moment the main focus of Yosys lies on the high-level aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used by Yosys to perform advanced gate-level optimizations.
An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced by Yosys in this tests where successfully verified using formal verification and are comparable in quality to the results produced by a commercial synthesis tool.
This document was originally published as bachelor thesis at the Vienna University of Technology [Wol13].
- 1. Introduction
- 2. Basic principles
- 3. Approach
- 4. Implementation overview
- 5. Internal cell library
- 6. Programming Yosys extensions
- 7. The Verilog and AST frontends
- 8. Optimizations
- 9. Technology mapping
- 10. Memory mapping
- Auxiliary libraries
- Auxiliary programs
- RTLIL text representation
- 010: Converting Verilog to BLIF page
- 011: Interactive design investigation page
- 012: Converting Verilog to BTOR page
- Literature references