Loading a design

keyword: Frontends

• read_verilog - read modules from Verilog file

read_verilog file1.v
read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
read_verilog -lib cell_library.v

verilog_defaults -add -I include_dir
read_verilog file3.v
read_verilog file4.v
verilog_defaults -clear

verilog_defaults -push
verilog_defaults -add -I include_dir
read_verilog file5.v
read_verilog file6.v
verilog_defaults -pop

Others:

• read - load HDL designs

• GHDL plugin for VHDL

• read_rtlil - read modules from RTLIL file (direct textual representation of Yosys internal state)

• read_aiger - read AIGER file

• read_blif - read BLIF file

• read_json - read JSON file

• read_liberty - read cells from liberty file