write_edif - write design to EDIF netlist file

yosys> help write_edif
write_edif [options] [filename]
Write the current design to an EDIF netlist file.
-top top_module
set the specified module as design top module
do not create "GND" and "VCC" cells. (this will produce an error
if the design contains constant nets. use "hilomap" to map to custom
constant drivers first)
create "GND" and "VCC" cells with "Y" outputs. (the default is
"G" for "GND" and "P" for "VCC".)
create EDIF properties for cell attributes
create extra KEEP nets by allowing a cell to drive multiple nets.
-pvector {par|bra|ang}
sets the delimiting character for module port rename clauses to
parentheses, square brackets, or angle brackets.
use index 0 for the LSB bit of a net or port instead of MSB.
Unfortunately there are different "flavors" of the EDIF file format. This
command generates EDIF files for the Xilinx place&route tools. It might be
necessary to make small modifications to this command when a different tool
is targeted.