Internal flow

A (usually short) synthesis script controls Yosys.

These scripts contain three types of commands:

• Frontends, that read input files (usually Verilog);

• Passes, that perform transformations on the design in memory;

• Backends, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, …).

• Flow overview
• Control and data flow
• The Verilog and AST frontends
  • Transforming Verilog to AST
    • The Verilog preprocessor
    • The Verilog lexer
    • The Verilog parser
  • Transforming AST to RTLIL
    • AST simplification
    • Generating RTLIL
  • Synthesizing Verilog always blocks
    • The ProcessGenerator algorithm
    • The proc pass