Latch cells

The cell types $_DLATCH_N_ and $_DLATCH_P_ represent d-type latches.

Table 15 Cell types for basic latches

Verilog	Cell Type
always @* if (!E) Q <= D	$_DLATCH_N_
always @* if (E) Q <= D	$_DLATCH_P_

The cell types $_DLATCH_[NP][NP][01]_ implement d-type latches with reset. The values in the table for these cell types relate to the following Verilog code template:

always @*
   if (R == RST_LVL)
      Q <= RST_VAL;
   else if (E == EN_LVL)
      Q <= D;

Table 16 Cell types for gate level logic networks (latches with reset)

\(EnLvl\)	\(RstLvl\)	\(RstVal\)	Cell Type
0	0	0	$_DLATCH_NN0_
0	0	1	$_DLATCH_NN1_
0	1	0	$_DLATCH_NP0_
0	1	1	$_DLATCH_NP1_
1	0	0	$_DLATCH_PN0_
1	0	1	$_DLATCH_PN1_
1	1	0	$_DLATCH_PP0_
1	1	1	$_DLATCH_PP1_

The cell types $_DLATCHSR_[NP][NP][NP]_ implement d-type latches with set and reset. The values in the table for these cell types relate to the following Verilog code template:

always @*
   if (R == RST_LVL)
      Q <= 0;
   else if (S == SET_LVL)
      Q <= 1;
   else if (E == EN_LVL)
      Q <= D;

Table 17 Cell types for gate level logic networks (latches with set and reset)

\(EnLvl\)	\(SetLvl\)	\(RstLvl\)	Cell Type
0	0	0	$_DLATCHSR_NNN_
0	0	1	$_DLATCHSR_NNP_
0	1	0	$_DLATCHSR_NPN_
0	1	1	$_DLATCHSR_NPP_
1	0	0	$_DLATCHSR_PNN_
1	0	1	$_DLATCHSR_PNP_
1	1	0	$_DLATCHSR_PPN_
1	1	1	$_DLATCHSR_PPP_

The cell types $_SR_[NP][NP]_ implement sr-type latches. The values in the table for these cell types relate to the following Verilog code template:

always @*
   if (R == RST_LVL)
      Q <= 0;
   else if (S == SET_LVL)
      Q <= 1;

Table 18 Cell types for gate level logic networks (SR latches)

\(SetLvl\)	\(RstLvl\)	Cell Type
0	0	$_SR_NN_
0	1	$_SR_NP_
1	0	$_SR_PN_
1	1	$_SR_PP_

yosys> help $_DLATCHSR_NNN_

A negative enable D-type latch with negative polarity set and negative polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 0 - | 0
                - 0 - - | 1
                0 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 377 simcells.v

module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCHSR_NNP_

A negative enable D-type latch with negative polarity set and positive polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 1 - | 0
                - 0 - - | 1
                0 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 378 simcells.v

module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCHSR_NPN_

A negative enable D-type latch with positive polarity set and negative polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 0 - | 0
                - 1 - - | 1
                0 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 379 simcells.v

module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCHSR_NPP_

A negative enable D-type latch with positive polarity set and positive polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 1 - | 0
                - 1 - - | 1
                0 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 380 simcells.v

module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCHSR_PNN_

A positive enable D-type latch with negative polarity set and negative polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 0 - | 0
                - 0 - - | 1
                1 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 381 simcells.v

module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCHSR_PNP_

A positive enable D-type latch with negative polarity set and positive polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 1 - | 0
                - 0 - - | 1
                1 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 382 simcells.v

module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCHSR_PPN_

A positive enable D-type latch with positive polarity set and negative polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 0 - | 0
                - 1 - - | 1
                1 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 383 simcells.v

module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCHSR_PPP_

A positive enable D-type latch with positive polarity set and positive polarity reset.

Truth table:    E S R D | Q
               ---------+---
                - - 1 - | 0
                - 1 - - | 1
                1 - - d | d
                - - - - | q

Simulation model (verilog)

Listing 384 simcells.v

module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
    input E, S, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_NN0_

A negative enable D-type latch with negative polarity reset.

Truth table:    E R D | Q
               -------+---
                - 0 - | 0
                0 - d | d
                - - - | q

Simulation model (verilog)

Listing 385 simcells.v

module \$_DLATCH_NN0_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
                    Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_NN1_

A negative enable D-type latch with negative polarity set.

Truth table:    E R D | Q
               -------+---
                - 0 - | 1
                0 - d | d
                - - - | q

Simulation model (verilog)

Listing 386 simcells.v

module \$_DLATCH_NN1_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
                    Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_NP0_

A negative enable D-type latch with positive polarity reset.

Truth table:    E R D | Q
               -------+---
                - 1 - | 0
                0 - d | d
                - - - | q

Simulation model (verilog)

Listing 387 simcells.v

module \$_DLATCH_NP0_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
                    Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_NP1_

A negative enable D-type latch with positive polarity set.

Truth table:    E R D | Q
               -------+---
                - 1 - | 1
                0 - d | d
                - - - | q

Simulation model (verilog)

Listing 388 simcells.v

module \$_DLATCH_NP1_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
                    Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_N_

A negative enable D-type latch.

Truth table:    E D | Q
               -----+---
                0 d | d
                - - | q

Simulation model (verilog)

Listing 389 simcells.v

module \$_DLATCH_N_ (E, D, Q);
    input E, D;
    output reg Q;
    always @* begin
        if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_PN0_

A positive enable D-type latch with negative polarity reset.

Truth table:    E R D | Q
               -------+---
                - 0 - | 0
                1 - d | d
                - - - | q

Simulation model (verilog)

Listing 390 simcells.v

module \$_DLATCH_PN0_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
                    Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_PN1_

A positive enable D-type latch with negative polarity set.

Truth table:    E R D | Q
               -------+---
                - 0 - | 1
                1 - d | d
                - - - | q

Simulation model (verilog)

Listing 391 simcells.v

module \$_DLATCH_PN1_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 0)
                    Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_PP0_

A positive enable D-type latch with positive polarity reset.

Truth table:    E R D | Q
               -------+---
                - 1 - | 0
                1 - d | d
                - - - | q

Simulation model (verilog)

Listing 392 simcells.v

module \$_DLATCH_PP0_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
                    Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_PP1_

A positive enable D-type latch with positive polarity set.

Truth table:    E R D | Q
               -------+---
                - 1 - | 1
                1 - d | d
                - - - | q

Simulation model (verilog)

Listing 393 simcells.v

module \$_DLATCH_PP1_ (E, R, D, Q);
    input E, R, D;
    output reg Q;
    always @* begin
        if (R == 1)
                    Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_P_

A positive enable D-type latch.

Truth table:    E D | Q
               -----+---
                1 d | d
                - - | q

Simulation model (verilog)

Listing 394 simcells.v

module \$_DLATCH_P_ (E, D, Q);
    input E, D;
    output reg Q;
    always @* begin
        if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SR_NN_

A set-reset latch with negative polarity SET and negative polarity RESET.

Truth table:    S R | Q
               -----+---
                - 0 | 0
                0 - | 1
                - - | q

Simulation model (verilog)

Listing 395 simcells.v

module \$_SR_NN_ (S, R, Q);
    input S, R;
    output reg Q;
    always @* begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
    end
endmodule

yosys> help $_SR_NP_

A set-reset latch with negative polarity SET and positive polarity RESET.

Truth table:    S R | Q
               -----+---
                - 1 | 0
                0 - | 1
                - - | q

Simulation model (verilog)

Listing 396 simcells.v

module \$_SR_NP_ (S, R, Q);
    input S, R;
    output reg Q;
    always @* begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
    end
endmodule

yosys> help $_SR_PN_

A set-reset latch with positive polarity SET and negative polarity RESET.

Truth table:    S R | Q
               -----+---
                - 0 | 0
                1 - | 1
                - - | q

Simulation model (verilog)

Listing 397 simcells.v

module \$_SR_PN_ (S, R, Q);
    input S, R;
    output reg Q;
    always @* begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
    end
endmodule

yosys> help $_SR_PP_

A set-reset latch with positive polarity SET and positive polarity RESET.

Truth table:    S R | Q
               -----+---
                - 1 | 0
                1 - | 1
                - - | q

Simulation model (verilog)

Listing 398 simcells.v

module \$_SR_PP_ (S, R, Q);
    input S, R;
    output reg Q;
    always @* begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
    end
endmodule