Internal cell library

The intermediate language used by Yosys (RTLIL) represents logic and memory with a series of cells. This section provides details for those cells, breaking them down into two major categories: coarse-grain word-level cells; and fine-grain gate-level cells. An additional section contains a list of properties which may be shared across multiple cells.

• Word-level cells
  • Unary operators
  • Binary operators
  • Multiplexers
  • Registers
  • Memories
  • Finite state machines
  • Coarse arithmetics
  • Arbitrary logic functions
  • Specify rules
  • Formal verification cells
  • Debugging cells
  • Wire cells
• Gate-level cells
  • Combinatorial cells (simple)
  • Combinatorial cells (combined)
  • Flip-flop cells
  • Latch cells
  • Other gate-level cells
• Cell properties
  • is_evaluable
  • x-aware
  • x-output