Yosys internals

Yosys is an extensible open source hardware synthesis tool. It is aimed at designers who are looking for an easily accessible, universal, and vendor-independent synthesis tool, as well as scientists who do research in electronic design automation (EDA) and are looking for an open synthesis framework that can be used to test algorithms on complex real-world designs.

Yosys can synthesize a large subset of Verilog 2005 and has been tested with a wide range of real-world designs, including the OpenRISC 1200 CPU, the openMSP430 CPU, the OpenCores I2C master, and the k68 CPU.

Yosys is written in C++, targeting C++11 at minimum. This chapter describes some of the fundamental Yosys data structures. For the sake of simplicity the C++ type names used in the Yosys implementation are used in this chapter, even though the chapter only explains the conceptual idea behind it and can be used as reference to implement a similar system in any language.

• Internal flow
  • Flow overview
  • Control and data flow
  • The Verilog and AST frontends
    • Transforming Verilog to AST
    • Transforming AST to RTLIL
    • Synthesizing Verilog always blocks
• Internal formats
  • Format overview
  • The RTL Intermediate Language (RTLIL)
    • RTLIL identifiers
    • RTLIL::Design and RTLIL::Module
    • RTLIL::Cell and RTLIL::Wire
    • RTLIL::SigSpec
    • RTLIL::Process
    • RTLIL::Memory
  • RTLIL text representation
    • Lexical elements
    • File
  • Internal cell library
    • RTL cells
    • Gates
• Extending Yosys
  • Writing extensions
    • Quick guide
    • The “stubnets” example module
  • Setting up a flow for ABC9
    • specify syntax
• Techmap by example
  • Mapping OR3X1
  • Conditional techmap
  • Scripting in map modules
  • Handling constant inputs
  • Handling shorted inputs
  • Notes on using techmap