Converting process blocks

The Verilog frontend converts always-blocks to RTL netlists for the expressions and “processess” for the control- and memory elements. The proc command then transforms these “processess” to netlists of RTL multiplexer and register cells. It also is a macro command that calls the other proc_* commands in a sensible order:

Listing 24 Passes called by proc

proc_clean # removes empty branches and processes
proc_rmdead # removes unreachable branches
proc_prune
proc_init # special handling of “initial” blocks
proc_arst # identifies modeling of async resets
proc_rom
proc_mux # converts decision trees to multiplexer networks
proc_dlatch
proc_dff # extracts registers from processes
proc_memwr
proc_clean # this should remove all the processes, provided all went fine
opt_expr -keepdc

After all the proc_* commands, opt_expr is called. This can be disabled by calling proc -noopt. For more information about proc, such as disabling certain sub commands, see proc - translate processes to netlists.

Many commands can not operate on modules with “processess” in them. Usually a call to proc is the first command in the actual synthesis procedure after design elaboration.

Example

docs/source/code_examples/synth_flow.

Listing 25 proc_01.v

module test(input D, C, R, output reg Q);
    always @(posedge C, posedge R)
        if (R)
	    Q <= 0;
	else
	    Q <= D;
endmodule

Listing 26 proc_01.ys

read_verilog proc_01.v
hierarchy -check -top test
proc;;

Listing 27 proc_02.v

module test(input D, C, R, RV,
            output reg Q);
    always @(posedge C, posedge R)
        if (R)
	    Q <= RV;
	else
	    Q <= D;
endmodule

Listing 28 proc_02.ys

read_verilog proc_02.v
hierarchy -check -top test
proc;;

Listing 29 proc_03.ys

read_verilog proc_03.v
hierarchy -check -top test
proc;;

Listing 30 proc_03.v

module test(input A, B, C, D, E,
            output reg Y);
    always @* begin
	Y <= A;
	if (B)
	    Y <= C;
	if (D)
	    Y <= E;
    end
endmodule