Mapping to cell libraries

While much of this documentation focuses on the use of Yosys with FPGAs, it is also possible to map to cell libraries which can be used in designing ASICs. This section will cover a brief example project, available in the Yosys source code under docs/source/code_examples/intro/. The project contains a simple ASIC synthesis script (counter.ys), a digital design written in Verilog (counter.v), and a simple CMOS cell library (mycells.lib). Many of the early steps here are already covered in more detail in the Synthesis starter document.


The counter.ys script includes the commands used to generate the images in this document. Code snippets in this document skip these commands; including line numbers to allow the reader to follow along with the source.

To learn more about these commands, check out A look at the show command.

A simple counter

First, let’s quickly look at the design:

Listing 55 counter.v
 1module counter (clk, rst, en, count);
 3	input clk, rst, en;
 4	output reg [1:0] count;
 6	always @(posedge clk)
 7		if (rst)
 8			count <= 2'd0;
 9		else if (en)
10			count <= count + 2'd1;

This is a simple counter with reset and enable. If the reset signal, rst, is high then the counter will reset to 0. Otherwise, if the enable signal, en, is high then the count register will increment by 1 each rising edge of the clock, clk.

Loading the design

Listing 56 counter.ys - read design
1# read design
2read_verilog counter.v
3hierarchy -check -top counter

Our circuit now looks like this:


Fig. 27 counter after hierarchy

Coarse-grain representation

Listing 57 counter.ys - the high-level stuff
 7# the high-level stuff
 8proc; opt
 9memory; opt
10fsm; opt

Fig. 28 Coarse-grain representation of the counter module

Logic gate mapping

Listing 58 counter.ys - mapping to internal cell library
14# mapping to internal cell library
15techmap; opt

Fig. 29 counter after techmap

Mapping to hardware

For this example, we are using a Liberty file to describe a cell library which our internal cell library will be mapped to:

Listing 59 mycells.lib
 1library(demo) {
 2  cell(BUF) {
 3    area: 6;
 4    pin(A) { direction: input; }
 5    pin(Y) { direction: output;
 6              function: "A"; }
 7  }
 8  cell(NOT) {
 9    area: 3;
10    pin(A) { direction: input; }
11    pin(Y) { direction: output;
12              function: "A'"; }
13  }
14  cell(NAND) {
15    area: 4;
16    pin(A) { direction: input; }
17    pin(B) { direction: input; }
18    pin(Y) { direction: output;
19             function: "(A*B)'"; }
20  }
21  cell(NOR) {
22    area: 4;
23    pin(A) { direction: input; }
24    pin(B) { direction: input; }
25    pin(Y) { direction: output;
26             function: "(A+B)'"; }
27  }
28  cell(DFF) {
29    area: 18;
30    ff(IQ, IQN) { clocked_on: C;
31                  next_state: D; }
32    pin(C) { direction: input;
33                 clock: true; }
34    pin(D) { direction: input; }
35    pin(Q) { direction: output;
36              function: "IQ"; }
37  }

Recall that the Yosys built-in logic gate types are $_NOT_, $_AND_, $_OR_, $_XOR_, and $_MUX_ with an assortment of dff memory types. mycells.lib defines our target cells as BUF, NOT, NAND, NOR, and DFF. Mapping between these is performed with the commands dfflibmap and abc as follows:

Listing 60 counter.ys - mapping to hardware
20dfflibmap -liberty mycells.lib
22# mapping logic to mycells.lib
23abc -liberty mycells.lib
25# cleanup

The final version of our counter module looks like this:


Fig. 30 counter after hardware cell mapping

Before finally being output as a verilog file with write_verilog, which can then be loaded into another tool:

Listing 61 counter.ys - write synthesized design
30# write synthesized design
31write_verilog synth.v