Literature references



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IEEE Standards Association and others. Ieee standard for vhdl register transfer level (rtl) synthesis. IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999), 2004. doi:10.1109/IEEESTD.2004.94802.


IEEE Standards Association and others. Ieee standard for verilog hardware description language. IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001), 2006. doi:10.1109/IEEESTD.2006.99495.


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Johann Glaser and C. Wolf. Methodology and example-driven interconnect synthesis for designing heterogeneous coarse-grain reconfigurable architectures. In Jan Haase, editor, Advances in Models, Methods, and Tools for Complex Chip Design — Selected contributions from FDL'12. Springer, 2013.


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C. Wolf. Design and implementation of the yosys open synthesis suite. Bachelor Thesis, Vienna University of Technology, 2013.


C. Wolf, Johann Glaser, Florian Schupfer, Jan Haase, and Christoph Grimm. Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic. In FDL Proceeding of the 2012 Forum on Specification and Design Languages, 194–201. 2012.