Literature references#

Bibliography

[ASU86]

Alfred V. Aho, Ravi Sethi, and Jeffrey D. Ullman. Compilers: principles, techniques, and tools. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1986. ISBN 0-201-10088-6.

[A+02]

IEEE Standards Association and others. Ieee standard for verilog register transfer level synthesis. IEEE Std 1364.1-2002, 2002. doi:10.1109/IEEESTD.2002.94220.

[A+04]

IEEE Standards Association and others. Ieee standard for vhdl register transfer level (rtl) synthesis. IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999), 2004. doi:10.1109/IEEESTD.2004.94802.

[A+06]

IEEE Standards Association and others. Ieee standard for verilog hardware description language. IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001), 2006. doi:10.1109/IEEESTD.2006.99495.

[A+09]

IEEE Standards Association and others. Ieee standard vhdl language reference manual. IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002), 26 2009. doi:10.1109/IEEESTD.2009.4772740.

[A+10]

IEEE Standards Association and others. Ieee standard for ip-xact, standard structure for packaging, integrating, and reusing ip within tools flows. IEEE Std 1685-2009, pages C1–360, 2010. doi:10.1109/IEEESTD.2010.5417309.

[BHSV90]

R.K. Brayton, G.D. Hachtel, and A.L. Sangiovanni-Vincentelli. Multilevel logic synthesis. Proceedings of the IEEE, 78(2):264–300, 1990. doi:10.1109/5.52213.

[CI00]

Clifford E. Cummings and Sunburst Design Inc. Nonblocking assignments in verilog synthesis, coding styles that kill. In SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper. 2000.

[EenSorensson03]

Niklas Eén and Niklas Sörensson. Temporal induction by incremental sat solving. Electronic Notes in Theoretical Computer Science, 89(4):543–560, 2003.

[GW13]

Johann Glaser and C. Wolf. Methodology and example-driven interconnect synthesis for designing heterogeneous coarse-grain reconfigurable architectures. In Jan Haase, editor, Advances in Models, Methods, and Tools for Complex Chip Design — Selected contributions from FDL'12. Springer, 2013.

[HS96]

G D Hachtel and F Somenzi. Logic synthesis and verification algorithms. 1996.

[LHBB85]

Kyu Y. Lee, Michael Holley, Mary Bailey, and Walter Bright. A high-level design language for programmable logic devices. VLSI Design (Manhasset NY: CPM Publications), pages 50–62, June 1985.

[STGR10]

Yiqiong Shi, Chan Wai Ting, Bah-Hwee Gwee, and Ye Ren. A highly efficient method for extracting fsms from flattened gate-level netlist. In Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2610–2613. 2010. doi:10.1109/ISCAS.2010.5537093.

[Ull76]

J. R. Ullmann. An algorithm for subgraph isomorphism. J. ACM, 23(1):31–42, January 1976. doi:10.1145/321921.321925.

[Wol13]

C. Wolf. Design and implementation of the yosys open synthesis suite. Bachelor Thesis, Vienna University of Technology, 2013.

[WGS+12]

C. Wolf, Johann Glaser, Florian Schupfer, Jan Haase, and Christoph Grimm. Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic. In FDL Proceeding of the 2012 Forum on Specification and Design Languages, 194–201. 2012.