Multiplexers

Multiplexers are generated by the Verilog HDL frontend for ?:-expressions. Multiplexers are also generated by the proc pass to map the decision trees from RTLIL::Process objects to logic.

The simplest multiplexer cell type is $mux. Cells of this type have a WITDH parameter and data inputs A and B and a data output Y, all of the specified width. This cell also has a single bit control input S. If S is 0 the value from the input A is sent to the output, if it is 1 the value from the B input is sent to the output. So the $mux cell implements the function Y = S ? B : A.

The $pmux cell is used to multiplex between many inputs using a one-hot select signal. Cells of this type have a WIDTH and a S_WIDTH parameter and inputs A, B, and S and an output Y. The S input is S_WIDTH bits wide. The A input and the output are both WIDTH bits wide and the B input is WIDTH*S_WIDTH bits wide. When all bits of S are zero, the value from A input is sent to the output. If the \(n\)‘th bit from S is set, the value \(n\)‘th WIDTH bits wide slice of the B input is sent to the output. When more than one bit from S is set the output is undefined. Cells of this type are used to model “parallel cases” (defined by using the parallel_case attribute, the unique or unique0 SystemVerilog keywords, or detected by an optimization).

The $tribuf cell is used to implement tristate logic. Cells of this type have a WIDTH parameter and inputs A and EN and an output Y. The A input and Y output are WIDTH bits wide, and the EN input is one bit wide. When EN is 0, the output is not driven. When EN is 1, the value from A input is sent to the Y output. Therefore, the $tribuf cell implements the function Y = EN ? A : 'bz.

Behavioural code with cascaded if-then-else- and case-statements usually results in trees of multiplexer cells. Many passes (from various optimizations to FSM extraction) heavily depend on these multiplexer trees to understand dependencies between signals. Therefore optimizations should not break these multiplexer trees (e.g. by replacing a multiplexer between a calculated signal and a constant zero with an $and gate).

yosys> help $bmux

Binary-encoded multiplexer

Selects between ‘slices’ of A where each value of S corresponds to a unique slice.

Properties:

is_evaluable

Simulation model (verilog)

Listing 188 simlib.v

module \$bmux (A, S, Y);

    parameter WIDTH = 0;
    parameter S_WIDTH = 0;

    input [(WIDTH << S_WIDTH)-1:0] A;
    input [S_WIDTH-1:0] S;
    output [WIDTH-1:0] Y;

    wire [WIDTH-1:0] bm0_out, bm1_out;

    generate
        if (S_WIDTH > 1) begin:muxlogic
            \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));
            \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));
            assign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;
        end else if (S_WIDTH == 1) begin:simple
            assign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];
        end else begin:passthru
            assign Y = A;
        end
    endgenerate

endmodule

yosys> help $bwmux

Bit-wise multiplexer

Equivalent to a series of 1-bit wide $mux cells.

Properties:

is_evaluable

Simulation model (verilog)

Listing 189 simlib.v

module \$bwmux (A, B, S, Y);

    parameter WIDTH = 0;

    input [WIDTH-1:0] A, B;
    input [WIDTH-1:0] S;
    output [WIDTH-1:0] Y;

    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i + 1) begin:slices
            assign Y[i] = S[i] ? B[i] : A[i];
        end
    endgenerate

endmodule

yosys> help $demux

Demultiplexer i.e routing single input to several outputs based on select signal. Unselected outputs are driven to zero.

Properties:

is_evaluable

Simulation model (verilog)

Listing 190 simlib.v

module \$demux (A, S, Y);

    parameter WIDTH = 1;
    parameter S_WIDTH = 1;

    input [WIDTH-1:0] A;
    input [S_WIDTH-1:0] S;
    output [(WIDTH << S_WIDTH)-1:0] Y;

    genvar i;
    generate
        for (i = 0; i < (1 << S_WIDTH); i = i + 1) begin:slices
            assign Y[i*WIDTH+:WIDTH] = (S == i) ? A : 0;
        end
    endgenerate

endmodule

yosys> help $mux

Multiplexer i.e selecting between two inputs based on select signal.

Properties:

is_evaluable

Simulation model (verilog)

Listing 191 simlib.v

module \$mux (A, B, S, Y);

    parameter WIDTH = 0;

    input [WIDTH-1:0] A, B;
    input S;
    output [WIDTH-1:0] Y;

    assign Y = S ? B : A;

endmodule

yosys> help $pmux

Priority-encoded multiplexer

Selects between ‘slices’ of B where each slice corresponds to a single bit of S. Outputs A when all bits of S are low.

Properties:

• is_evaluable

• x-output

Simulation model (verilog)

Listing 192 simlib.v

module \$pmux (A, B, S, Y);

    parameter WIDTH = 0;
    parameter S_WIDTH = 0;

    input [WIDTH-1:0] A;
    input [WIDTH*S_WIDTH-1:0] B;
    input [S_WIDTH-1:0] S;
    output reg [WIDTH-1:0] Y;

    integer i;
    reg found_active_sel_bit;

    always @* begin
        Y = A;
        found_active_sel_bit = 0;
        for (i = 0; i < S_WIDTH; i = i+1)
            case (S[i])
                1'b1: begin
                    Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i);
                    found_active_sel_bit = 1;
                end
                1'b0: ;
                1'bx: begin
                    Y = 'bx;
                    found_active_sel_bit = 'bx;
                end
            endcase
    end

endmodule

yosys> help $tribuf

A tri-state buffer. This buffer conditionally drives the output with the value of the input based on the enable signal.

Simulation model (verilog)

Listing 193 simlib.v

module \$tribuf (A, EN, Y);

    parameter WIDTH = 0;

    input [WIDTH-1:0] A;
    input EN;
    output [WIDTH-1:0] Y;

    assign Y = EN ? A : 'bz;

endmodule