Binary operators

All binary RTL cells have two input ports A and B and one output port Y. They also have the following parameters:

A_SIGNED

Set to a non-zero value if the input A is signed and therefore should be sign-extended when needed.

A_WIDTH

The width of the input port A.

B_SIGNED

Set to a non-zero value if the input B is signed and therefore should be sign-extended when needed.

B_WIDTH

The width of the input port B.

Y_WIDTH

The width of the output port Y.

Table 5 Cell types for binary operators with their corresponding Verilog expressions.

Verilog

Cell Type

Verilog

Cell Type

Y = A & B

$and

Y = A ** B

$pow

Y = A | B

$or

Y = A < B

$lt

Y = A ^ B

$xor

Y = A <= B

$le

Y = A ~^ B

$xnor

Y = A == B

$eq

Y = A << B

$shl

Y = A != B

$ne

Y = A >> B

$shr

Y = A >= B

$ge

Y = A <<< B

$sshl

Y = A > B

$gt

Y = A >>> B

$sshr

Y = A + B

$add

Y = A && B

$logic_and

Y = A - B

$sub

Y = A || B

$logic_or

Y = A * B

$mul

Y = A === B

$eqx

Y = A / B

$div

Y = A !== B

$nex

Y = A % B

$mod

N/A

$shift

N/A

$divfloor

N/A

$shiftx

N/A

$modfloor

The $shl and $shr cells implement logical shifts, whereas the $sshl and $sshr cells implement arithmetic shifts. The $shl and $sshl cells implement the same operation. All four of these cells interpret the second operand as unsigned, and require B_SIGNED to be zero.

Two additional shift operator cells are available that do not directly correspond to any operator in Verilog, $shift and $shiftx. The $shift cell performs a right logical shift if the second operand is positive (or unsigned), and a left logical shift if it is negative. The $shiftx cell performs the same operation as the $shift cell, but the vacated bit positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.

For the binary cells that output a logical value ($logic_and, $logic_or, $eqx, $nex, $lt, $le, $eq, $ne, $ge, $gt), when the Y_WIDTH parameter is greater than 1, the output is zero-extended, and only the least significant bit varies.

Division and modulo cells are available in two rounding modes. The original $div and $mod cells are based on truncating division, and correspond to the semantics of the verilog / and % operators. The $divfloor and $modfloor cells represent flooring division and flooring modulo, the latter of which corresponds to the % operator in Python. See the following table for a side-by-side comparison between the different semantics.

Table 6 Comparison between different rounding modes for division and modulo cells.

Division

Result

Truncating

Flooring

$div

$mod

$divfloor

$modfloor

-10 / 3

-3.3

-3

-1

-4

2

10 / -3

-3.3

-3

1

-4

-2

-10 / -3

3.3

3

-1

3

-1

10 / 3

3.3

3

1

3

1
yosys> help $add

Addition of inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘+’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 159 simlib.v
1004module \$add (A, B, Y);
1005
1006    parameter A_SIGNED = 0;
1007    parameter B_SIGNED = 0;
1008    parameter A_WIDTH = 0;
1009    parameter B_WIDTH = 0;
1010    parameter Y_WIDTH = 0;
1011
1012    input [A_WIDTH-1:0] A;
1013    input [B_WIDTH-1:0] B;
1014    output [Y_WIDTH-1:0] Y;
1015
1016    generate
1017        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1018            assign Y = $signed(A) + $signed(B);
1019        end else begin:BLOCK2
1020            assign Y = A + B;
1021        end
1022    endgenerate
1023
1024endmodule
yosys> help $and

A bit-wise AND. This corresponds to the Verilog ‘&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 160 simlib.v
177module \$and (A, B, Y);
178
179    parameter A_SIGNED = 0;
180    parameter B_SIGNED = 0;
181    parameter A_WIDTH = 0;
182    parameter B_WIDTH = 0;
183    parameter Y_WIDTH = 0;
184
185    input [A_WIDTH-1:0] A;
186    input [B_WIDTH-1:0] B;
187    output [Y_WIDTH-1:0] Y;
188
189    generate
190        if (A_SIGNED && B_SIGNED) begin:BLOCK1
191            assign Y = $signed(A) & $signed(B);
192        end else begin:BLOCK2
193            assign Y = A & B;
194        end
195    endgenerate
196
197endmodule
yosys> help $bweqx

Bit-wise case equality

A bit-wise version of $eqx.

Properties:
Simulation model (verilog)
Listing 161 simlib.v
2036module \$bweqx (A, B, Y);
2037
2038    parameter WIDTH = 0;
2039
2040    input [WIDTH-1:0] A, B;
2041    output [WIDTH-1:0] Y;
2042
2043    genvar i;
2044    generate
2045        for (i = 0; i < WIDTH; i = i + 1) begin:slices
2046            assign Y[i] = A[i] === B[i];
2047        end
2048    endgenerate
2049
2050endmodule
yosys> help $div

Divider

This corresponds to the Verilog ‘/’ operator, performing division and truncating the result (rounding towards 0).

Properties:
Simulation model (verilog)
Listing 162 simlib.v
1363module \$div (A, B, Y);
1364
1365    parameter A_SIGNED = 0;
1366    parameter B_SIGNED = 0;
1367    parameter A_WIDTH = 0;
1368    parameter B_WIDTH = 0;
1369    parameter Y_WIDTH = 0;
1370
1371    input [A_WIDTH-1:0] A;
1372    input [B_WIDTH-1:0] B;
1373    output [Y_WIDTH-1:0] Y;
1374
1375    generate
1376        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1377            assign Y = $signed(A) / $signed(B);
1378        end else begin:BLOCK2
1379            assign Y = A / B;
1380        end
1381    endgenerate
1382
1383endmodule
yosys> help $divfloor

Division with floored result (rounded towards negative infinity).

Properties:

is_evaluable

Simulation model (verilog)
Listing 163 simlib.v
1426module \$divfloor (A, B, Y);
1427
1428    parameter A_SIGNED = 0;
1429    parameter B_SIGNED = 0;
1430    parameter A_WIDTH = 0;
1431    parameter B_WIDTH = 0;
1432    parameter Y_WIDTH = 0;
1433
1434    input [A_WIDTH-1:0] A;
1435    input [B_WIDTH-1:0] B;
1436    output [Y_WIDTH-1:0] Y;
1437
1438    generate
1439        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1440            localparam WIDTH =
1441                    A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
1442                    B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
1443            wire [WIDTH:0] A_buf, B_buf, N_buf;
1444            assign A_buf = $signed(A);
1445            assign B_buf = $signed(B);
1446            assign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));
1447            assign Y = $signed(N_buf) / $signed(B_buf);
1448        end else begin:BLOCK2
1449            assign Y = A / B;
1450        end
1451    endgenerate
1452
1453endmodule
yosys> help $eq

An equality comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘==’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 164 simlib.v
813module \$eq (A, B, Y);
814
815    parameter A_SIGNED = 0;
816    parameter B_SIGNED = 0;
817    parameter A_WIDTH = 0;
818    parameter B_WIDTH = 0;
819    parameter Y_WIDTH = 0;
820
821    input [A_WIDTH-1:0] A;
822    input [B_WIDTH-1:0] B;
823    output [Y_WIDTH-1:0] Y;
824
825    generate
826        if (A_SIGNED && B_SIGNED) begin:BLOCK1
827            assign Y = $signed(A) == $signed(B);
828        end else begin:BLOCK2
829            assign Y = A == B;
830        end
831    endgenerate
832
833endmodule
yosys> help $eqx

Case equality

An exact equality comparison between inputs ‘A’ and ‘B’. Also known as the case equality operator. This corresponds to the Verilog ‘===’ operator. Unlike equality comparison that can give ‘x’ as output, an exact equality comparison will strictly give ‘0’ or ‘1’ as output, even if input includes ‘x’ or ‘z’ values.

Properties:
Simulation model (verilog)
Listing 165 simlib.v
878module \$eqx (A, B, Y);
879
880    parameter A_SIGNED = 0;
881    parameter B_SIGNED = 0;
882    parameter A_WIDTH = 0;
883    parameter B_WIDTH = 0;
884    parameter Y_WIDTH = 0;
885
886    input [A_WIDTH-1:0] A;
887    input [B_WIDTH-1:0] B;
888    output [Y_WIDTH-1:0] Y;
889
890    generate
891        if (A_SIGNED && B_SIGNED) begin:BLOCK1
892            assign Y = $signed(A) === $signed(B);
893        end else begin:BLOCK2
894            assign Y = A === B;
895        end
896    endgenerate
897
898endmodule
yosys> help $ge

A greater-than-or-equal-to comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘>=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 166 simlib.v
941module \$ge (A, B, Y);
942
943    parameter A_SIGNED = 0;
944    parameter B_SIGNED = 0;
945    parameter A_WIDTH = 0;
946    parameter B_WIDTH = 0;
947    parameter Y_WIDTH = 0;
948
949    input [A_WIDTH-1:0] A;
950    input [B_WIDTH-1:0] B;
951    output [Y_WIDTH-1:0] Y;
952
953    generate
954        if (A_SIGNED && B_SIGNED) begin:BLOCK1
955            assign Y = $signed(A) >= $signed(B);
956        end else begin:BLOCK2
957            assign Y = A >= B;
958        end
959    endgenerate
960
961endmodule
yosys> help $gt

A greater-than comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 167 simlib.v
973module \$gt (A, B, Y);
974
975    parameter A_SIGNED = 0;
976    parameter B_SIGNED = 0;
977    parameter A_WIDTH = 0;
978    parameter B_WIDTH = 0;
979    parameter Y_WIDTH = 0;
980
981    input [A_WIDTH-1:0] A;
982    input [B_WIDTH-1:0] B;
983    output [Y_WIDTH-1:0] Y;
984
985    generate
986        if (A_SIGNED && B_SIGNED) begin:BLOCK1
987            assign Y = $signed(A) > $signed(B);
988        end else begin:BLOCK2
989            assign Y = A > B;
990        end
991    endgenerate
992
993endmodule
yosys> help $le

A less-than-or-equal-to comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘<=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 168 simlib.v
781module \$le (A, B, Y);
782
783    parameter A_SIGNED = 0;
784    parameter B_SIGNED = 0;
785    parameter A_WIDTH = 0;
786    parameter B_WIDTH = 0;
787    parameter Y_WIDTH = 0;
788
789    input [A_WIDTH-1:0] A;
790    input [B_WIDTH-1:0] B;
791    output [Y_WIDTH-1:0] Y;
792
793    generate
794        if (A_SIGNED && B_SIGNED) begin:BLOCK1
795            assign Y = $signed(A) <= $signed(B);
796        end else begin:BLOCK2
797            assign Y = A <= B;
798        end
799    endgenerate
800
801endmodule
yosys> help $logic_and

A logical AND. This corresponds to the Verilog ‘&&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 169 simlib.v
1572module \$logic_and (A, B, Y);
1573
1574    parameter A_SIGNED = 0;
1575    parameter B_SIGNED = 0;
1576    parameter A_WIDTH = 0;
1577    parameter B_WIDTH = 0;
1578    parameter Y_WIDTH = 0;
1579
1580    input [A_WIDTH-1:0] A;
1581    input [B_WIDTH-1:0] B;
1582    output [Y_WIDTH-1:0] Y;
1583
1584    generate
1585        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1586            assign Y = $signed(A) && $signed(B);
1587        end else begin:BLOCK2
1588            assign Y = A && B;
1589        end
1590    endgenerate
1591
1592endmodule
yosys> help $logic_or

A logical OR. This corresponds to the Verilog ‘||’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 170 simlib.v
1603module \$logic_or (A, B, Y);
1604
1605    parameter A_SIGNED = 0;
1606    parameter B_SIGNED = 0;
1607    parameter A_WIDTH = 0;
1608    parameter B_WIDTH = 0;
1609    parameter Y_WIDTH = 0;
1610
1611    input [A_WIDTH-1:0] A;
1612    input [B_WIDTH-1:0] B;
1613    output [Y_WIDTH-1:0] Y;
1614
1615    generate
1616        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1617            assign Y = $signed(A) || $signed(B);
1618        end else begin:BLOCK2
1619            assign Y = A || B;
1620        end
1621    endgenerate
1622
1623endmodule
yosys> help $lt

A less-than comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 171 simlib.v
749module \$lt (A, B, Y);
750
751    parameter A_SIGNED = 0;
752    parameter B_SIGNED = 0;
753    parameter A_WIDTH = 0;
754    parameter B_WIDTH = 0;
755    parameter Y_WIDTH = 0;
756
757    input [A_WIDTH-1:0] A;
758    input [B_WIDTH-1:0] B;
759    output [Y_WIDTH-1:0] Y;
760
761    generate
762        if (A_SIGNED && B_SIGNED) begin:BLOCK1
763            assign Y = $signed(A) < $signed(B);
764        end else begin:BLOCK2
765            assign Y = A < B;
766        end
767    endgenerate
768
769endmodule
yosys> help $mod

Modulo

This corresponds to the Verilog ‘%’ operator, giving the module (or remainder) of division and truncating the result (rounding towards 0).

Invariant: $div(A, B) * B + $mod(A, B) == A

Properties:
Simulation model (verilog)
Listing 172 simlib.v
1395module \$mod (A, B, Y);
1396
1397    parameter A_SIGNED = 0;
1398    parameter B_SIGNED = 0;
1399    parameter A_WIDTH = 0;
1400    parameter B_WIDTH = 0;
1401    parameter Y_WIDTH = 0;
1402
1403    input [A_WIDTH-1:0] A;
1404    input [B_WIDTH-1:0] B;
1405    output [Y_WIDTH-1:0] Y;
1406
1407    generate
1408        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1409            assign Y = $signed(A) % $signed(B);
1410        end else begin:BLOCK2
1411            assign Y = A % B;
1412        end
1413    endgenerate
1414
1415endmodule
yosys> help $modfloor

Modulo/remainder of division with floored result (rounded towards negative infinity).

Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A

Properties:

is_evaluable

Simulation model (verilog)
Listing 173 simlib.v
1466module \$modfloor (A, B, Y);
1467
1468    parameter A_SIGNED = 0;
1469    parameter B_SIGNED = 0;
1470    parameter A_WIDTH = 0;
1471    parameter B_WIDTH = 0;
1472    parameter Y_WIDTH = 0;
1473
1474    input [A_WIDTH-1:0] A;
1475    input [B_WIDTH-1:0] B;
1476    output [Y_WIDTH-1:0] Y;
1477
1478    generate
1479        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1480            localparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
1481            wire [WIDTH-1:0] B_buf, Y_trunc;
1482            assign B_buf = $signed(B);
1483            assign Y_trunc = $signed(A) % $signed(B);
1484            // flooring mod is the same as truncating mod for positive division results (A and B have
1485            // the same sign), as well as when there's no remainder.
1486            // For all other cases, they behave as `floor - trunc = B`
1487            assign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);
1488        end else begin:BLOCK2
1489            // no difference between truncating and flooring for unsigned
1490            assign Y = A % B;
1491        end
1492    endgenerate
1493
1494endmodule
yosys> help $mul

Multiplication of inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘*’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 174 simlib.v
1068module \$mul (A, B, Y);
1069
1070    parameter A_SIGNED = 0;
1071    parameter B_SIGNED = 0;
1072    parameter A_WIDTH = 0;
1073    parameter B_WIDTH = 0;
1074    parameter Y_WIDTH = 0;
1075
1076    input [A_WIDTH-1:0] A;
1077    input [B_WIDTH-1:0] B;
1078    output [Y_WIDTH-1:0] Y;
1079
1080    generate
1081        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1082            assign Y = $signed(A) * $signed(B);
1083        end else begin:BLOCK2
1084            assign Y = A * B;
1085        end
1086    endgenerate
1087
1088endmodule
yosys> help $ne

An inequality comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘!=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 175 simlib.v
845module \$ne (A, B, Y);
846
847    parameter A_SIGNED = 0;
848    parameter B_SIGNED = 0;
849    parameter A_WIDTH = 0;
850    parameter B_WIDTH = 0;
851    parameter Y_WIDTH = 0;
852
853    input [A_WIDTH-1:0] A;
854    input [B_WIDTH-1:0] B;
855    output [Y_WIDTH-1:0] Y;
856
857    generate
858        if (A_SIGNED && B_SIGNED) begin:BLOCK1
859            assign Y = $signed(A) != $signed(B);
860        end else begin:BLOCK2
861            assign Y = A != B;
862        end
863    endgenerate
864
865endmodule
yosys> help $nex

Case inequality

This corresponds to the Verilog ‘!==’ operator.

Refer to $eqx for more details.

Properties:
Simulation model (verilog)
Listing 176 simlib.v
909module \$nex (A, B, Y);
910
911    parameter A_SIGNED = 0;
912    parameter B_SIGNED = 0;
913    parameter A_WIDTH = 0;
914    parameter B_WIDTH = 0;
915    parameter Y_WIDTH = 0;
916
917    input [A_WIDTH-1:0] A;
918    input [B_WIDTH-1:0] B;
919    output [Y_WIDTH-1:0] Y;
920
921    generate
922        if (A_SIGNED && B_SIGNED) begin:BLOCK1
923            assign Y = $signed(A) !== $signed(B);
924        end else begin:BLOCK2
925            assign Y = A !== B;
926        end
927    endgenerate
928
929endmodule
yosys> help $or

A bit-wise OR. This corresponds to the Verilog ‘|’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 177 simlib.v
208module \$or (A, B, Y);
209
210    parameter A_SIGNED = 0;
211    parameter B_SIGNED = 0;
212    parameter A_WIDTH = 0;
213    parameter B_WIDTH = 0;
214    parameter Y_WIDTH = 0;
215
216    input [A_WIDTH-1:0] A;
217    input [B_WIDTH-1:0] B;
218    output [Y_WIDTH-1:0] Y;
219
220    generate
221        if (A_SIGNED && B_SIGNED) begin:BLOCK1
222            assign Y = $signed(A) | $signed(B);
223        end else begin:BLOCK2
224            assign Y = A | B;
225        end
226    endgenerate
227
228endmodule
yosys> help $pow

Exponentiation of an input (Y = A ** B). This corresponds to the Verilog ‘**’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 178 simlib.v
1508module \$pow (A, B, Y);
1509
1510    parameter A_SIGNED = 0;
1511    parameter B_SIGNED = 0;
1512    parameter A_WIDTH = 0;
1513    parameter B_WIDTH = 0;
1514    parameter Y_WIDTH = 0;
1515
1516    input [A_WIDTH-1:0] A;
1517    input [B_WIDTH-1:0] B;
1518    output [Y_WIDTH-1:0] Y;
1519
1520    generate
1521        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1522            assign Y = $signed(A) ** $signed(B);
1523        end else if (A_SIGNED) begin:BLOCK2
1524            assign Y = $signed(A) ** B;
1525        end else if (B_SIGNED) begin:BLOCK3
1526            assign Y = A ** $signed(B);
1527        end else begin:BLOCK4
1528            assign Y = A ** B;
1529        end
1530    endgenerate
1531
1532endmodule
yosys> help $shift

Variable shifter

Performs a right logical shift if the second operand is positive (or unsigned), and a left logical shift if it is negative.

Properties:

is_evaluable

Simulation model (verilog)
Listing 179 simlib.v
566module \$shift (A, B, Y);
567
568    parameter A_SIGNED = 0;
569    parameter B_SIGNED = 0;
570    parameter A_WIDTH = 0;
571    parameter B_WIDTH = 0;
572    parameter Y_WIDTH = 0;
573
574    input [A_WIDTH-1:0] A;
575    input [B_WIDTH-1:0] B;
576    output [Y_WIDTH-1:0] Y;
577
578    generate
579        if (A_SIGNED) begin:BLOCK1
580            if (B_SIGNED) begin:BLOCK2
581                assign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;
582            end else begin:BLOCK3
583                assign Y = $signed(A) >> B;
584            end
585        end else begin:BLOCK4
586            if (B_SIGNED) begin:BLOCK5
587                assign Y = $signed(B) < 0 ? A << -B : A >> B;
588            end else begin:BLOCK6
589                assign Y = A >> B;
590            end
591        end
592    endgenerate
593
594endmodule
yosys> help $shiftx

Indexed part-select

Same as the $shift cell, but fills with ‘x’.

Properties:
Simulation model (verilog)
Listing 180 simlib.v
603module \$shiftx (A, B, Y);
604
605    parameter A_SIGNED = 0;
606    parameter B_SIGNED = 0;
607    parameter A_WIDTH = 0;
608    parameter B_WIDTH = 0;
609    parameter Y_WIDTH = 0;
610
611    input [A_WIDTH-1:0] A;
612    input [B_WIDTH-1:0] B;
613    output [Y_WIDTH-1:0] Y;
614
615    generate
616        if (Y_WIDTH > 0)
617            if (B_SIGNED) begin:BLOCK1
618                assign Y = A[$signed(B) +: Y_WIDTH];
619            end else begin:BLOCK2
620                assign Y = A[B +: Y_WIDTH];
621            end
622    endgenerate
623
624endmodule
yosys> help $shl

A logical shift-left operation. This corresponds to the Verilog ‘<<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 181 simlib.v
442module \$shl (A, B, Y);
443
444    parameter A_SIGNED = 0;
445    parameter B_SIGNED = 0;
446    parameter A_WIDTH = 0;
447    parameter B_WIDTH = 0;
448    parameter Y_WIDTH = 0;
449
450    input [A_WIDTH-1:0] A;
451    input [B_WIDTH-1:0] B;
452    output [Y_WIDTH-1:0] Y;
453
454    generate
455        if (A_SIGNED) begin:BLOCK1
456            assign Y = $signed(A) << B;
457        end else begin:BLOCK2
458            assign Y = A << B;
459        end
460    endgenerate
461
462endmodule
yosys> help $shr

A logical shift-right operation. This corresponds to the Verilog ‘>>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 182 simlib.v
473module \$shr (A, B, Y);
474
475    parameter A_SIGNED = 0;
476    parameter B_SIGNED = 0;
477    parameter A_WIDTH = 0;
478    parameter B_WIDTH = 0;
479    parameter Y_WIDTH = 0;
480
481    input [A_WIDTH-1:0] A;
482    input [B_WIDTH-1:0] B;
483    output [Y_WIDTH-1:0] Y;
484
485    generate
486        if (A_SIGNED) begin:BLOCK1
487            assign Y = $signed(A) >> B;
488        end else begin:BLOCK2
489            assign Y = A >> B;
490        end
491    endgenerate
492
493endmodule
yosys> help $sshl

An arithmatic shift-left operation. This corresponds to the Verilog ‘<<<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 183 simlib.v
505module \$sshl (A, B, Y);
506
507    parameter A_SIGNED = 0;
508    parameter B_SIGNED = 0;
509    parameter A_WIDTH = 0;
510    parameter B_WIDTH = 0;
511    parameter Y_WIDTH = 0;
512
513    input [A_WIDTH-1:0] A;
514    input [B_WIDTH-1:0] B;
515    output [Y_WIDTH-1:0] Y;
516
517    generate
518        if (A_SIGNED) begin:BLOCK1
519            assign Y = $signed(A) <<< B;
520        end else begin:BLOCK2
521            assign Y = A <<< B;
522        end
523    endgenerate
524
525endmodule
yosys> help $sshr

An arithmatic shift-right operation. This corresponds to the Verilog ‘>>>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 184 simlib.v
537module \$sshr (A, B, Y);
538
539    parameter A_SIGNED = 0;
540    parameter B_SIGNED = 0;
541    parameter A_WIDTH = 0;
542    parameter B_WIDTH = 0;
543    parameter Y_WIDTH = 0;
544
545    input [A_WIDTH-1:0] A;
546    input [B_WIDTH-1:0] B;
547    output [Y_WIDTH-1:0] Y;
548
549    generate
550        if (A_SIGNED) begin:BLOCK1
551            assign Y = $signed(A) >>> B;
552        end else begin:BLOCK2
553            assign Y = A >>> B;
554        end
555    endgenerate
556
557endmodule
yosys> help $sub

Subtraction between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘-’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 185 simlib.v
1036module \$sub (A, B, Y);
1037
1038    parameter A_SIGNED = 0;
1039    parameter B_SIGNED = 0;
1040    parameter A_WIDTH = 0;
1041    parameter B_WIDTH = 0;
1042    parameter Y_WIDTH = 0;
1043
1044    input [A_WIDTH-1:0] A;
1045    input [B_WIDTH-1:0] B;
1046    output [Y_WIDTH-1:0] Y;
1047
1048    generate
1049        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1050            assign Y = $signed(A) - $signed(B);
1051        end else begin:BLOCK2
1052            assign Y = A - B;
1053        end
1054    endgenerate
1055
1056endmodule
yosys> help $xnor

A bit-wise XNOR. This corresponds to the Verilog ‘~^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 186 simlib.v
270module \$xnor (A, B, Y);
271
272    parameter A_SIGNED = 0;
273    parameter B_SIGNED = 0;
274    parameter A_WIDTH = 0;
275    parameter B_WIDTH = 0;
276    parameter Y_WIDTH = 0;
277
278    input [A_WIDTH-1:0] A;
279    input [B_WIDTH-1:0] B;
280    output [Y_WIDTH-1:0] Y;
281
282    generate
283        if (A_SIGNED && B_SIGNED) begin:BLOCK1
284            assign Y = $signed(A) ~^ $signed(B);
285        end else begin:BLOCK2
286            assign Y = A ~^ B;
287        end
288    endgenerate
289
290endmodule
yosys> help $xor

A bit-wise XOR. This corresponds to the Verilog ‘^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 187 simlib.v
239module \$xor (A, B, Y);
240
241    parameter A_SIGNED = 0;
242    parameter B_SIGNED = 0;
243    parameter A_WIDTH = 0;
244    parameter B_WIDTH = 0;
245    parameter Y_WIDTH = 0;
246
247    input [A_WIDTH-1:0] A;
248    input [B_WIDTH-1:0] B;
249    output [Y_WIDTH-1:0] Y;
250
251    generate
252        if (A_SIGNED && B_SIGNED) begin:BLOCK1
253            assign Y = $signed(A) ^ $signed(B);
254        end else begin:BLOCK2
255            assign Y = A ^ B;
256        end
257    endgenerate
258
259endmodule