Binary operators

All binary RTL cells have two input ports A and B and one output port Y. They also have the following parameters:

A_SIGNED

Set to a non-zero value if the input A is signed and therefore should be sign-extended when needed.

A_WIDTH

The width of the input port A.

B_SIGNED

Set to a non-zero value if the input B is signed and therefore should be sign-extended when needed.

B_WIDTH

The width of the input port B.

Y_WIDTH

The width of the output port Y.

Table 5 Cell types for binary operators with their corresponding Verilog expressions.

Verilog

Cell Type

Verilog

Cell Type

Y = A & B

$and

Y = A ** B

$pow

Y = A | B

$or

Y = A < B

$lt

Y = A ^ B

$xor

Y = A <= B

$le

Y = A ~^ B

$xnor

Y = A == B

$eq

Y = A << B

$shl

Y = A != B

$ne

Y = A >> B

$shr

Y = A >= B

$ge

Y = A <<< B

$sshl

Y = A > B

$gt

Y = A >>> B

$sshr

Y = A + B

$add

Y = A && B

$logic_and

Y = A - B

$sub

Y = A || B

$logic_or

Y = A * B

$mul

Y = A === B

$eqx

Y = A / B

$div

Y = A !== B

$nex

Y = A % B

$mod

N/A

$shift

N/A

$divfloor

N/A

$shiftx

N/A

$modfloor

The $shl and $shr cells implement logical shifts, whereas the $sshl and $sshr cells implement arithmetic shifts. The $shl and $sshl cells implement the same operation. All four of these cells interpret the second operand as unsigned, and require B_SIGNED to be zero.

Two additional shift operator cells are available that do not directly correspond to any operator in Verilog, $shift and $shiftx. The $shift cell performs a right logical shift if the second operand is positive (or unsigned), and a left logical shift if it is negative. The $shiftx cell performs the same operation as the $shift cell, but the vacated bit positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.

For the binary cells that output a logical value ($logic_and, $logic_or, $eqx, $nex, $lt, $le, $eq, $ne, $ge, $gt), when the Y_WIDTH parameter is greater than 1, the output is zero-extended, and only the least significant bit varies.

Division and modulo cells are available in two rounding modes. The original $div and $mod cells are based on truncating division, and correspond to the semantics of the verilog / and % operators. The $divfloor and $modfloor cells represent flooring division and flooring modulo, the latter of which corresponds to the % operator in Python. See the following table for a side-by-side comparison between the different semantics.

Table 6 Comparison between different rounding modes for division and modulo cells.

Division

Result

Truncating

Flooring

$div

$mod

$divfloor

$modfloor

-10 / 3

-3.3

-3

-1

-4

2

10 / -3

-3.3

-3

1

-4

-2

-10 / -3

3.3

3

-1

3

-1

10 / 3

3.3

3

1

3

1
yosys> help $add

Addition of inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘+’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 124 simlib.v
973module \$add (A, B, Y);
974
975    parameter A_SIGNED = 0;
976    parameter B_SIGNED = 0;
977    parameter A_WIDTH = 0;
978    parameter B_WIDTH = 0;
979    parameter Y_WIDTH = 0;
980
981    input [A_WIDTH-1:0] A;
982    input [B_WIDTH-1:0] B;
983    output [Y_WIDTH-1:0] Y;
984
985    generate
986        if (A_SIGNED && B_SIGNED) begin:BLOCK1
987            assign Y = $signed(A) + $signed(B);
988        end else begin:BLOCK2
989            assign Y = A + B;
990        end
991    endgenerate
992
993endmodule
yosys> help $and

A bit-wise AND. This corresponds to the Verilog ‘&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 125 simlib.v
146module \$and (A, B, Y);
147
148    parameter A_SIGNED = 0;
149    parameter B_SIGNED = 0;
150    parameter A_WIDTH = 0;
151    parameter B_WIDTH = 0;
152    parameter Y_WIDTH = 0;
153
154    input [A_WIDTH-1:0] A;
155    input [B_WIDTH-1:0] B;
156    output [Y_WIDTH-1:0] Y;
157
158    generate
159        if (A_SIGNED && B_SIGNED) begin:BLOCK1
160            assign Y = $signed(A) & $signed(B);
161        end else begin:BLOCK2
162            assign Y = A & B;
163        end
164    endgenerate
165
166endmodule
yosys> help $bweqx

Bit-wise case equality

A bit-wise version of $eqx.

Properties:
Simulation model (verilog)
Listing 126 simlib.v
1891module \$bweqx (A, B, Y);
1892
1893    parameter WIDTH = 0;
1894
1895    input [WIDTH-1:0] A, B;
1896    output [WIDTH-1:0] Y;
1897
1898    genvar i;
1899    generate
1900        for (i = 0; i < WIDTH; i = i + 1) begin:slices
1901            assign Y[i] = A[i] === B[i];
1902        end
1903    endgenerate
1904
1905endmodule
yosys> help $div

Divider

This corresponds to the Verilog ‘/’ operator, performing division and truncating the result (rounding towards 0).

Properties:
Simulation model (verilog)
Listing 127 simlib.v
1218module \$div (A, B, Y);
1219
1220    parameter A_SIGNED = 0;
1221    parameter B_SIGNED = 0;
1222    parameter A_WIDTH = 0;
1223    parameter B_WIDTH = 0;
1224    parameter Y_WIDTH = 0;
1225
1226    input [A_WIDTH-1:0] A;
1227    input [B_WIDTH-1:0] B;
1228    output [Y_WIDTH-1:0] Y;
1229
1230    generate
1231        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1232            assign Y = $signed(A) / $signed(B);
1233        end else begin:BLOCK2
1234            assign Y = A / B;
1235        end
1236    endgenerate
1237
1238endmodule
yosys> help $divfloor

Division with floored result (rounded towards negative infinity).

Properties:

is_evaluable

Simulation model (verilog)
Listing 128 simlib.v
1281module \$divfloor (A, B, Y);
1282
1283    parameter A_SIGNED = 0;
1284    parameter B_SIGNED = 0;
1285    parameter A_WIDTH = 0;
1286    parameter B_WIDTH = 0;
1287    parameter Y_WIDTH = 0;
1288
1289    input [A_WIDTH-1:0] A;
1290    input [B_WIDTH-1:0] B;
1291    output [Y_WIDTH-1:0] Y;
1292
1293    generate
1294        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1295            localparam WIDTH =
1296                    A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
1297                    B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
1298            wire [WIDTH:0] A_buf, B_buf, N_buf;
1299            assign A_buf = $signed(A);
1300            assign B_buf = $signed(B);
1301            assign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));
1302            assign Y = $signed(N_buf) / $signed(B_buf);
1303        end else begin:BLOCK2
1304            assign Y = A / B;
1305        end
1306    endgenerate
1307
1308endmodule
yosys> help $eq

An equality comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘==’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 129 simlib.v
782module \$eq (A, B, Y);
783
784    parameter A_SIGNED = 0;
785    parameter B_SIGNED = 0;
786    parameter A_WIDTH = 0;
787    parameter B_WIDTH = 0;
788    parameter Y_WIDTH = 0;
789
790    input [A_WIDTH-1:0] A;
791    input [B_WIDTH-1:0] B;
792    output [Y_WIDTH-1:0] Y;
793
794    generate
795        if (A_SIGNED && B_SIGNED) begin:BLOCK1
796            assign Y = $signed(A) == $signed(B);
797        end else begin:BLOCK2
798            assign Y = A == B;
799        end
800    endgenerate
801
802endmodule
yosys> help $eqx

Case equality

An exact equality comparison between inputs ‘A’ and ‘B’. Also known as the case equality operator. This corresponds to the Verilog ‘===’ operator. Unlike equality comparison that can give ‘x’ as output, an exact equality comparison will strictly give ‘0’ or ‘1’ as output, even if input includes ‘x’ or ‘z’ values.

Properties:
Simulation model (verilog)
Listing 130 simlib.v
847module \$eqx (A, B, Y);
848
849    parameter A_SIGNED = 0;
850    parameter B_SIGNED = 0;
851    parameter A_WIDTH = 0;
852    parameter B_WIDTH = 0;
853    parameter Y_WIDTH = 0;
854
855    input [A_WIDTH-1:0] A;
856    input [B_WIDTH-1:0] B;
857    output [Y_WIDTH-1:0] Y;
858
859    generate
860        if (A_SIGNED && B_SIGNED) begin:BLOCK1
861            assign Y = $signed(A) === $signed(B);
862        end else begin:BLOCK2
863            assign Y = A === B;
864        end
865    endgenerate
866
867endmodule
yosys> help $ge

A greater-than-or-equal-to comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘>=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 131 simlib.v
910module \$ge (A, B, Y);
911
912    parameter A_SIGNED = 0;
913    parameter B_SIGNED = 0;
914    parameter A_WIDTH = 0;
915    parameter B_WIDTH = 0;
916    parameter Y_WIDTH = 0;
917
918    input [A_WIDTH-1:0] A;
919    input [B_WIDTH-1:0] B;
920    output [Y_WIDTH-1:0] Y;
921
922    generate
923        if (A_SIGNED && B_SIGNED) begin:BLOCK1
924            assign Y = $signed(A) >= $signed(B);
925        end else begin:BLOCK2
926            assign Y = A >= B;
927        end
928    endgenerate
929
930endmodule
yosys> help $gt

A greater-than comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 132 simlib.v
942module \$gt (A, B, Y);
943
944    parameter A_SIGNED = 0;
945    parameter B_SIGNED = 0;
946    parameter A_WIDTH = 0;
947    parameter B_WIDTH = 0;
948    parameter Y_WIDTH = 0;
949
950    input [A_WIDTH-1:0] A;
951    input [B_WIDTH-1:0] B;
952    output [Y_WIDTH-1:0] Y;
953
954    generate
955        if (A_SIGNED && B_SIGNED) begin:BLOCK1
956            assign Y = $signed(A) > $signed(B);
957        end else begin:BLOCK2
958            assign Y = A > B;
959        end
960    endgenerate
961
962endmodule
yosys> help $le

A less-than-or-equal-to comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘<=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 133 simlib.v
750module \$le (A, B, Y);
751
752    parameter A_SIGNED = 0;
753    parameter B_SIGNED = 0;
754    parameter A_WIDTH = 0;
755    parameter B_WIDTH = 0;
756    parameter Y_WIDTH = 0;
757
758    input [A_WIDTH-1:0] A;
759    input [B_WIDTH-1:0] B;
760    output [Y_WIDTH-1:0] Y;
761
762    generate
763        if (A_SIGNED && B_SIGNED) begin:BLOCK1
764            assign Y = $signed(A) <= $signed(B);
765        end else begin:BLOCK2
766            assign Y = A <= B;
767        end
768    endgenerate
769
770endmodule
yosys> help $logic_and

A logical AND. This corresponds to the Verilog ‘&&’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 134 simlib.v
1427module \$logic_and (A, B, Y);
1428
1429    parameter A_SIGNED = 0;
1430    parameter B_SIGNED = 0;
1431    parameter A_WIDTH = 0;
1432    parameter B_WIDTH = 0;
1433    parameter Y_WIDTH = 0;
1434
1435    input [A_WIDTH-1:0] A;
1436    input [B_WIDTH-1:0] B;
1437    output [Y_WIDTH-1:0] Y;
1438
1439    generate
1440        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1441            assign Y = $signed(A) && $signed(B);
1442        end else begin:BLOCK2
1443            assign Y = A && B;
1444        end
1445    endgenerate
1446
1447endmodule
yosys> help $logic_or

A logical OR. This corresponds to the Verilog ‘||’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 135 simlib.v
1458module \$logic_or (A, B, Y);
1459
1460    parameter A_SIGNED = 0;
1461    parameter B_SIGNED = 0;
1462    parameter A_WIDTH = 0;
1463    parameter B_WIDTH = 0;
1464    parameter Y_WIDTH = 0;
1465
1466    input [A_WIDTH-1:0] A;
1467    input [B_WIDTH-1:0] B;
1468    output [Y_WIDTH-1:0] Y;
1469
1470    generate
1471        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1472            assign Y = $signed(A) || $signed(B);
1473        end else begin:BLOCK2
1474            assign Y = A || B;
1475        end
1476    endgenerate
1477
1478endmodule
yosys> help $lt

A less-than comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 136 simlib.v
718module \$lt (A, B, Y);
719
720    parameter A_SIGNED = 0;
721    parameter B_SIGNED = 0;
722    parameter A_WIDTH = 0;
723    parameter B_WIDTH = 0;
724    parameter Y_WIDTH = 0;
725
726    input [A_WIDTH-1:0] A;
727    input [B_WIDTH-1:0] B;
728    output [Y_WIDTH-1:0] Y;
729
730    generate
731        if (A_SIGNED && B_SIGNED) begin:BLOCK1
732            assign Y = $signed(A) < $signed(B);
733        end else begin:BLOCK2
734            assign Y = A < B;
735        end
736    endgenerate
737
738endmodule
yosys> help $mod

Modulo

This corresponds to the Verilog ‘%’ operator, giving the module (or remainder) of division and truncating the result (rounding towards 0).

Invariant: $div(A, B) * B + $mod(A, B) == A

Properties:
Simulation model (verilog)
Listing 137 simlib.v
1250module \$mod (A, B, Y);
1251
1252    parameter A_SIGNED = 0;
1253    parameter B_SIGNED = 0;
1254    parameter A_WIDTH = 0;
1255    parameter B_WIDTH = 0;
1256    parameter Y_WIDTH = 0;
1257
1258    input [A_WIDTH-1:0] A;
1259    input [B_WIDTH-1:0] B;
1260    output [Y_WIDTH-1:0] Y;
1261
1262    generate
1263        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1264            assign Y = $signed(A) % $signed(B);
1265        end else begin:BLOCK2
1266            assign Y = A % B;
1267        end
1268    endgenerate
1269
1270endmodule
yosys> help $modfloor

Modulo/remainder of division with floored result (rounded towards negative infinity).

Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A

Properties:

is_evaluable

Simulation model (verilog)
Listing 138 simlib.v
1321module \$modfloor (A, B, Y);
1322
1323    parameter A_SIGNED = 0;
1324    parameter B_SIGNED = 0;
1325    parameter A_WIDTH = 0;
1326    parameter B_WIDTH = 0;
1327    parameter Y_WIDTH = 0;
1328
1329    input [A_WIDTH-1:0] A;
1330    input [B_WIDTH-1:0] B;
1331    output [Y_WIDTH-1:0] Y;
1332
1333    generate
1334        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1335            localparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
1336            wire [WIDTH-1:0] B_buf, Y_trunc;
1337            assign B_buf = $signed(B);
1338            assign Y_trunc = $signed(A) % $signed(B);
1339            // flooring mod is the same as truncating mod for positive division results (A and B have
1340            // the same sign), as well as when there's no remainder.
1341            // For all other cases, they behave as `floor - trunc = B`
1342            assign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);
1343        end else begin:BLOCK2
1344            // no difference between truncating and flooring for unsigned
1345            assign Y = A % B;
1346        end
1347    endgenerate
1348
1349endmodule
yosys> help $mul

Multiplication of inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘*’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 139 simlib.v
1037module \$mul (A, B, Y);
1038
1039    parameter A_SIGNED = 0;
1040    parameter B_SIGNED = 0;
1041    parameter A_WIDTH = 0;
1042    parameter B_WIDTH = 0;
1043    parameter Y_WIDTH = 0;
1044
1045    input [A_WIDTH-1:0] A;
1046    input [B_WIDTH-1:0] B;
1047    output [Y_WIDTH-1:0] Y;
1048
1049    generate
1050        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1051            assign Y = $signed(A) * $signed(B);
1052        end else begin:BLOCK2
1053            assign Y = A * B;
1054        end
1055    endgenerate
1056
1057endmodule
yosys> help $ne

An inequality comparison between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘!=’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 140 simlib.v
814module \$ne (A, B, Y);
815
816    parameter A_SIGNED = 0;
817    parameter B_SIGNED = 0;
818    parameter A_WIDTH = 0;
819    parameter B_WIDTH = 0;
820    parameter Y_WIDTH = 0;
821
822    input [A_WIDTH-1:0] A;
823    input [B_WIDTH-1:0] B;
824    output [Y_WIDTH-1:0] Y;
825
826    generate
827        if (A_SIGNED && B_SIGNED) begin:BLOCK1
828            assign Y = $signed(A) != $signed(B);
829        end else begin:BLOCK2
830            assign Y = A != B;
831        end
832    endgenerate
833
834endmodule
yosys> help $nex

Case inequality

This corresponds to the Verilog ‘!==’ operator.

Refer to $eqx for more details.

Properties:
Simulation model (verilog)
Listing 141 simlib.v
878module \$nex (A, B, Y);
879
880    parameter A_SIGNED = 0;
881    parameter B_SIGNED = 0;
882    parameter A_WIDTH = 0;
883    parameter B_WIDTH = 0;
884    parameter Y_WIDTH = 0;
885
886    input [A_WIDTH-1:0] A;
887    input [B_WIDTH-1:0] B;
888    output [Y_WIDTH-1:0] Y;
889
890    generate
891        if (A_SIGNED && B_SIGNED) begin:BLOCK1
892            assign Y = $signed(A) !== $signed(B);
893        end else begin:BLOCK2
894            assign Y = A !== B;
895        end
896    endgenerate
897
898endmodule
yosys> help $or

A bit-wise OR. This corresponds to the Verilog ‘|’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 142 simlib.v
177module \$or (A, B, Y);
178
179    parameter A_SIGNED = 0;
180    parameter B_SIGNED = 0;
181    parameter A_WIDTH = 0;
182    parameter B_WIDTH = 0;
183    parameter Y_WIDTH = 0;
184
185    input [A_WIDTH-1:0] A;
186    input [B_WIDTH-1:0] B;
187    output [Y_WIDTH-1:0] Y;
188
189    generate
190        if (A_SIGNED && B_SIGNED) begin:BLOCK1
191            assign Y = $signed(A) | $signed(B);
192        end else begin:BLOCK2
193            assign Y = A | B;
194        end
195    endgenerate
196
197endmodule
yosys> help $pow

Exponentiation of an input (Y = A ** B). This corresponds to the Verilog ‘**’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 143 simlib.v
1363module \$pow (A, B, Y);
1364
1365    parameter A_SIGNED = 0;
1366    parameter B_SIGNED = 0;
1367    parameter A_WIDTH = 0;
1368    parameter B_WIDTH = 0;
1369    parameter Y_WIDTH = 0;
1370
1371    input [A_WIDTH-1:0] A;
1372    input [B_WIDTH-1:0] B;
1373    output [Y_WIDTH-1:0] Y;
1374
1375    generate
1376        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1377            assign Y = $signed(A) ** $signed(B);
1378        end else if (A_SIGNED) begin:BLOCK2
1379            assign Y = $signed(A) ** B;
1380        end else if (B_SIGNED) begin:BLOCK3
1381            assign Y = A ** $signed(B);
1382        end else begin:BLOCK4
1383            assign Y = A ** B;
1384        end
1385    endgenerate
1386
1387endmodule
yosys> help $shift

Variable shifter

Performs a right logical shift if the second operand is positive (or unsigned), and a left logical shift if it is negative.

Properties:

is_evaluable

Simulation model (verilog)
Listing 144 simlib.v
535module \$shift (A, B, Y);
536
537    parameter A_SIGNED = 0;
538    parameter B_SIGNED = 0;
539    parameter A_WIDTH = 0;
540    parameter B_WIDTH = 0;
541    parameter Y_WIDTH = 0;
542
543    input [A_WIDTH-1:0] A;
544    input [B_WIDTH-1:0] B;
545    output [Y_WIDTH-1:0] Y;
546
547    generate
548        if (A_SIGNED) begin:BLOCK1
549            if (B_SIGNED) begin:BLOCK2
550                assign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;
551            end else begin:BLOCK3
552                assign Y = $signed(A) >> B;
553            end
554        end else begin:BLOCK4
555            if (B_SIGNED) begin:BLOCK5
556                assign Y = $signed(B) < 0 ? A << -B : A >> B;
557            end else begin:BLOCK6
558                assign Y = A >> B;
559            end
560        end
561    endgenerate
562
563endmodule
yosys> help $shiftx

Indexed part-select

Same as the $shift cell, but fills with ‘x’.

Properties:
Simulation model (verilog)
Listing 145 simlib.v
572module \$shiftx (A, B, Y);
573
574    parameter A_SIGNED = 0;
575    parameter B_SIGNED = 0;
576    parameter A_WIDTH = 0;
577    parameter B_WIDTH = 0;
578    parameter Y_WIDTH = 0;
579
580    input [A_WIDTH-1:0] A;
581    input [B_WIDTH-1:0] B;
582    output [Y_WIDTH-1:0] Y;
583
584    generate
585        if (Y_WIDTH > 0)
586            if (B_SIGNED) begin:BLOCK1
587                assign Y = A[$signed(B) +: Y_WIDTH];
588            end else begin:BLOCK2
589                assign Y = A[B +: Y_WIDTH];
590            end
591    endgenerate
592
593endmodule
yosys> help $shl

A logical shift-left operation. This corresponds to the Verilog ‘<<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 146 simlib.v
411module \$shl (A, B, Y);
412
413    parameter A_SIGNED = 0;
414    parameter B_SIGNED = 0;
415    parameter A_WIDTH = 0;
416    parameter B_WIDTH = 0;
417    parameter Y_WIDTH = 0;
418
419    input [A_WIDTH-1:0] A;
420    input [B_WIDTH-1:0] B;
421    output [Y_WIDTH-1:0] Y;
422
423    generate
424        if (A_SIGNED) begin:BLOCK1
425            assign Y = $signed(A) << B;
426        end else begin:BLOCK2
427            assign Y = A << B;
428        end
429    endgenerate
430
431endmodule
yosys> help $shr

A logical shift-right operation. This corresponds to the Verilog ‘>>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 147 simlib.v
442module \$shr (A, B, Y);
443
444    parameter A_SIGNED = 0;
445    parameter B_SIGNED = 0;
446    parameter A_WIDTH = 0;
447    parameter B_WIDTH = 0;
448    parameter Y_WIDTH = 0;
449
450    input [A_WIDTH-1:0] A;
451    input [B_WIDTH-1:0] B;
452    output [Y_WIDTH-1:0] Y;
453
454    generate
455        if (A_SIGNED) begin:BLOCK1
456            assign Y = $signed(A) >> B;
457        end else begin:BLOCK2
458            assign Y = A >> B;
459        end
460    endgenerate
461
462endmodule
yosys> help $sshl

An arithmatic shift-left operation. This corresponds to the Verilog ‘<<<’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 148 simlib.v
474module \$sshl (A, B, Y);
475
476    parameter A_SIGNED = 0;
477    parameter B_SIGNED = 0;
478    parameter A_WIDTH = 0;
479    parameter B_WIDTH = 0;
480    parameter Y_WIDTH = 0;
481
482    input [A_WIDTH-1:0] A;
483    input [B_WIDTH-1:0] B;
484    output [Y_WIDTH-1:0] Y;
485
486    generate
487        if (A_SIGNED) begin:BLOCK1
488            assign Y = $signed(A) <<< B;
489        end else begin:BLOCK2
490            assign Y = A <<< B;
491        end
492    endgenerate
493
494endmodule
yosys> help $sshr

An arithmatic shift-right operation. This corresponds to the Verilog ‘>>>’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 149 simlib.v
506module \$sshr (A, B, Y);
507
508    parameter A_SIGNED = 0;
509    parameter B_SIGNED = 0;
510    parameter A_WIDTH = 0;
511    parameter B_WIDTH = 0;
512    parameter Y_WIDTH = 0;
513
514    input [A_WIDTH-1:0] A;
515    input [B_WIDTH-1:0] B;
516    output [Y_WIDTH-1:0] Y;
517
518    generate
519        if (A_SIGNED) begin:BLOCK1
520            assign Y = $signed(A) >>> B;
521        end else begin:BLOCK2
522            assign Y = A >>> B;
523        end
524    endgenerate
525
526endmodule
yosys> help $sub

Subtraction between inputs ‘A’ and ‘B’. This corresponds to the Verilog ‘-’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 150 simlib.v
1005module \$sub (A, B, Y);
1006
1007    parameter A_SIGNED = 0;
1008    parameter B_SIGNED = 0;
1009    parameter A_WIDTH = 0;
1010    parameter B_WIDTH = 0;
1011    parameter Y_WIDTH = 0;
1012
1013    input [A_WIDTH-1:0] A;
1014    input [B_WIDTH-1:0] B;
1015    output [Y_WIDTH-1:0] Y;
1016
1017    generate
1018        if (A_SIGNED && B_SIGNED) begin:BLOCK1
1019            assign Y = $signed(A) - $signed(B);
1020        end else begin:BLOCK2
1021            assign Y = A - B;
1022        end
1023    endgenerate
1024
1025endmodule
yosys> help $xnor

A bit-wise XNOR. This corresponds to the Verilog ‘~^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 151 simlib.v
239module \$xnor (A, B, Y);
240
241    parameter A_SIGNED = 0;
242    parameter B_SIGNED = 0;
243    parameter A_WIDTH = 0;
244    parameter B_WIDTH = 0;
245    parameter Y_WIDTH = 0;
246
247    input [A_WIDTH-1:0] A;
248    input [B_WIDTH-1:0] B;
249    output [Y_WIDTH-1:0] Y;
250
251    generate
252        if (A_SIGNED && B_SIGNED) begin:BLOCK1
253            assign Y = $signed(A) ~^ $signed(B);
254        end else begin:BLOCK2
255            assign Y = A ~^ B;
256        end
257    endgenerate
258
259endmodule
yosys> help $xor

A bit-wise XOR. This corresponds to the Verilog ‘^’ operator.

Properties:

is_evaluable

Simulation model (verilog)
Listing 152 simlib.v
208module \$xor (A, B, Y);
209
210    parameter A_SIGNED = 0;
211    parameter B_SIGNED = 0;
212    parameter A_WIDTH = 0;
213    parameter B_WIDTH = 0;
214    parameter Y_WIDTH = 0;
215
216    input [A_WIDTH-1:0] A;
217    input [B_WIDTH-1:0] B;
218    output [Y_WIDTH-1:0] Y;
219
220    generate
221        if (A_SIGNED && B_SIGNED) begin:BLOCK1
222            assign Y = $signed(A) ^ $signed(B);
223        end else begin:BLOCK2
224            assign Y = A ^ B;
225        end
226    endgenerate
227
228endmodule