Combinatorial cells (combined)

These cells combine two or more combinatorial cells (simple) into a single cell.

Table 8 Cell types for gate level combinatorial cells (combined)

Verilog

Cell Type

Y = A & ~B

$_ANDNOT_

Y = A | ~B

$_ORNOT_

Y = ~((A & B) | C)

$_AOI3_

Y = ~((A | B) & C)

$_OAI3_

Y = ~((A & B) | (C & D))

$_AOI4_

Y = ~((A | B) & (C | D))

$_OAI4_

Y = ~(S ? B : A)

$_NMUX_

(see below)

$_MUX4_

(see below)

$_MUX8_

(see below)

$_MUX16_

The $_MUX4_, $_MUX8_ and $_MUX16_ cells are used to model wide muxes, and correspond to the following Verilog code:

// $_MUX4_
assign Y = T ? (S ? D : C) :
               (S ? B : A);
// $_MUX8_
assign Y = U ? T ? (S ? H : G) :
                   (S ? F : E) :
               T ? (S ? D : C) :
                   (S ? B : A);
// $_MUX16_
assign Y = V ? U ? T ? (S ? P : O) :
                       (S ? N : M) :
                   T ? (S ? L : K) :
                       (S ? J : I) :
               U ? T ? (S ? H : G) :
                       (S ? F : E) :
                   T ? (S ? D : C) :
                       (S ? B : A);
yosys> help $_ANDNOT_

A 2-input AND-NOT gate.

Truth table:    A B | Y
               -----+---
                0 0 | 0
                0 1 | 0
                1 0 | 1
                1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 224 simcells.v
198module \$_ANDNOT_ (A, B, Y);
199    input A, B;
200    output Y;
201    assign Y = A & (~B);
202endmodule
yosys> help $_AOI3_

A 3-input And-Or-Invert gate.

Truth table:    A B C | Y
               -------+---
                0 0 0 | 1
                0 0 1 | 0
                0 1 0 | 1
                0 1 1 | 0
                1 0 0 | 1
                1 0 1 | 0
                1 1 0 | 0
                1 1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 225 simcells.v
367module \$_AOI3_ (A, B, C, Y);
368    input A, B, C;
369    output Y;
370    assign Y = ~((A & B) | C);
371endmodule
yosys> help $_AOI4_

A 4-input And-Or-Invert gate.

Truth table:    A B C D | Y
               ---------+---
                0 0 0 0 | 1
                0 0 0 1 | 1
                0 0 1 0 | 1
                0 0 1 1 | 0
                0 1 0 0 | 1
                0 1 0 1 | 1
                0 1 1 0 | 1
                0 1 1 1 | 0
                1 0 0 0 | 1
                1 0 0 1 | 1
                1 0 1 0 | 1
                1 0 1 1 | 0
                1 1 0 0 | 0
                1 1 0 1 | 0
                1 1 1 0 | 0
                1 1 1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 226 simcells.v
423module \$_AOI4_ (A, B, C, D, Y);
424    input A, B, C, D;
425    output Y;
426    assign Y = ~((A & B) | (C & D));
427endmodule
yosys> help $_MUX16_

A 16-input MUX gate.

Truth table:    A B C D E F G H I J K L M N O P S T U V | Y
               -----------------------------------------+---
                a - - - - - - - - - - - - - - - 0 0 0 0 | a
                - b - - - - - - - - - - - - - - 1 0 0 0 | b
                - - c - - - - - - - - - - - - - 0 1 0 0 | c
                - - - d - - - - - - - - - - - - 1 1 0 0 | d
                - - - - e - - - - - - - - - - - 0 0 1 0 | e
                - - - - - f - - - - - - - - - - 1 0 1 0 | f
                - - - - - - g - - - - - - - - - 0 1 1 0 | g
                - - - - - - - h - - - - - - - - 1 1 1 0 | h
                - - - - - - - - i - - - - - - - 0 0 0 1 | i
                - - - - - - - - - j - - - - - - 1 0 0 1 | j
                - - - - - - - - - - k - - - - - 0 1 0 1 | k
                - - - - - - - - - - - l - - - - 1 1 0 1 | l
                - - - - - - - - - - - - m - - - 0 0 1 1 | m
                - - - - - - - - - - - - - n - - 1 0 1 1 | n
                - - - - - - - - - - - - - - o - 0 1 1 1 | o
                - - - - - - - - - - - - - - - p 1 1 1 1 | p
Properties:

is_evaluable

Simulation model (verilog)
Listing 227 simcells.v
336module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
337    input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
338    output Y;
339    assign Y = V ? U ? T ? (S ? P : O) :
340                           (S ? N : M) :
341                       T ? (S ? L : K) :
342                           (S ? J : I) :
343                   U ? T ? (S ? H : G) :
344                           (S ? F : E) :
345                       T ? (S ? D : C) :
346                           (S ? B : A);
347endmodule
yosys> help $_MUX4_

A 4-input MUX gate.

Truth table:    A B C D S T | Y
               -------------+---
                a - - - 0 0 | a
                - b - - 1 0 | b
                - - c - 0 1 | c
                - - - d 1 1 | d
Properties:

is_evaluable

Simulation model (verilog)
Listing 228 simcells.v
276module \$_MUX4_ (A, B, C, D, S, T, Y);
277    input A, B, C, D, S, T;
278    output Y;
279    assign Y = T ? (S ? D : C) :
280                   (S ? B : A);
281endmodule
yosys> help $_MUX8_

An 8-input MUX gate.

Truth table:    A B C D E F G H S T U | Y
               -----------------------+---
                a - - - - - - - 0 0 0 | a
                - b - - - - - - 1 0 0 | b
                - - c - - - - - 0 1 0 | c
                - - - d - - - - 1 1 0 | d
                - - - - e - - - 0 0 1 | e
                - - - - - f - - 1 0 1 | f
                - - - - - - g - 0 1 1 | g
                - - - - - - - h 1 1 1 | h
Properties:

is_evaluable

Simulation model (verilog)
Listing 229 simcells.v
301module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
302    input A, B, C, D, E, F, G, H, S, T, U;
303    output Y;
304    assign Y = U ? T ? (S ? H : G) :
305                       (S ? F : E) :
306                   T ? (S ? D : C) :
307                       (S ? B : A);
308endmodule
yosys> help $_NMUX_

A 2-input inverting MUX gate.

Truth table:    A B S | Y
               -------+---
                0 - 0 | 1
                1 - 0 | 0
                - 0 1 | 1
                - 1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 230 simcells.v
256module \$_NMUX_ (A, B, S, Y);
257    input A, B, S;
258    output Y;
259    assign Y = S ? !B : !A;
260endmodule
yosys> help $_OAI3_

A 3-input Or-And-Invert gate.

Truth table:    A B C | Y
               -------+---
                0 0 0 | 1
                0 0 1 | 1
                0 1 0 | 1
                0 1 1 | 0
                1 0 0 | 1
                1 0 1 | 0
                1 1 0 | 1
                1 1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 231 simcells.v
391module \$_OAI3_ (A, B, C, Y);
392    input A, B, C;
393    output Y;
394    assign Y = ~((A | B) & C);
395endmodule
yosys> help $_OAI4_

A 4-input Or-And-Invert gate.

Truth table:    A B C D | Y
               ---------+---
                0 0 0 0 | 1
                0 0 0 1 | 1
                0 0 1 0 | 1
                0 0 1 1 | 1
                0 1 0 0 | 1
                0 1 0 1 | 0
                0 1 1 0 | 0
                0 1 1 1 | 0
                1 0 0 0 | 1
                1 0 0 1 | 0
                1 0 1 0 | 0
                1 0 1 1 | 0
                1 1 0 0 | 1
                1 1 0 1 | 0
                1 1 1 0 | 0
                1 1 1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 232 simcells.v
455module \$_OAI4_ (A, B, C, D, Y);
456    input A, B, C, D;
457    output Y;
458    assign Y = ~((A | B) & (C | D));
459endmodule
yosys> help $_ORNOT_

A 2-input OR-NOT gate.

Truth table:    A B | Y
               -----+---
                0 0 | 1
                0 1 | 0
                1 0 | 1
                1 1 | 1
Properties:

is_evaluable

Simulation model (verilog)
Listing 233 simcells.v
218module \$_ORNOT_ (A, B, Y);
219    input A, B;
220    output Y;
221    assign Y = A | (~B);
222endmodule