Combinatorial cells (simple)

Table 7 Cell types for gate level combinatorial cells (simple)

Verilog

Cell Type

Y = A

$_BUF_

Y = ~A

$_NOT_

Y = A & B

$_AND_

Y = ~(A & B)

$_NAND_

Y = A | B

$_OR_

Y = ~(A | B)

$_NOR_

Y = A ^ B

$_XOR_

Y = ~(A ^ B)

$_XNOR_

Y = S ? B : A

$_MUX_
yosys> help $_AND_

A 2-input AND gate.

Truth table:    A B | Y
               -----+---
                0 0 | 0
                0 1 | 0
                1 0 | 0
                1 1 | 1
Properties:

is_evaluable

Simulation model (verilog)
Listing 215 simcells.v
78module \$_AND_ (A, B, Y);
79    input A, B;
80    output Y;
81    assign Y = A & B;
82endmodule
yosys> help $_BUF_

A buffer. This cell type is always optimized away by the opt_clean pass.

Truth table:    A | Y
               ---+---
                0 | 0
                1 | 1
Properties:

is_evaluable

Simulation model (verilog)
Listing 216 simcells.v
40module \$_BUF_ (A, Y);
41    input A;
42    output Y;
43    assign Y = A;
44endmodule
yosys> help $_MUX_

A 2-input MUX gate.

Truth table:    A B S | Y
               -------+---
                a - 0 | a
                - b 1 | b
Properties:

is_evaluable

Simulation model (verilog)
Listing 217 simcells.v
236module \$_MUX_ (A, B, S, Y);
237    input A, B, S;
238    output Y;
239    assign Y = S ? B : A;
240endmodule
yosys> help $_NAND_

A 2-input NAND gate.

Truth table:    A B | Y
               -----+---
                0 0 | 1
                0 1 | 1
                1 0 | 1
                1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 218 simcells.v
 98module \$_NAND_ (A, B, Y);
 99    input A, B;
100    output Y;
101    assign Y = ~(A & B);
102endmodule
yosys> help $_NOR_

A 2-input NOR gate.

Truth table:    A B | Y
               -----+---
                0 0 | 1
                0 1 | 0
                1 0 | 0
                1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 219 simcells.v
138module \$_NOR_ (A, B, Y);
139    input A, B;
140    output Y;
141    assign Y = ~(A | B);
142endmodule
yosys> help $_NOT_

An inverter gate.

Truth table:    A | Y
               ---+---
                0 | 1
                1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 220 simcells.v
58module \$_NOT_ (A, Y);
59    input A;
60    output Y;
61    assign Y = ~A;
62endmodule
yosys> help $_OR_

A 2-input OR gate.

Truth table:    A B | Y
               -----+---
                0 0 | 0
                0 1 | 1
                1 0 | 1
                1 1 | 1
Properties:

is_evaluable

Simulation model (verilog)
Listing 221 simcells.v
118module \$_OR_ (A, B, Y);
119    input A, B;
120    output Y;
121    assign Y = A | B;
122endmodule
yosys> help $_XNOR_

A 2-input XNOR gate.

Truth table:    A B | Y
               -----+---
                0 0 | 1
                0 1 | 0
                1 0 | 0
                1 1 | 1
Properties:

is_evaluable

Simulation model (verilog)
Listing 222 simcells.v
178module \$_XNOR_ (A, B, Y);
179    input A, B;
180    output Y;
181    assign Y = ~(A ^ B);
182endmodule
yosys> help $_XOR_

A 2-input XOR gate.

Truth table:    A B | Y
               -----+---
                0 0 | 0
                0 1 | 1
                1 0 | 1
                1 1 | 0
Properties:

is_evaluable

Simulation model (verilog)
Listing 223 simcells.v
158module \$_XOR_ (A, B, Y);
159    input A, B;
160    output Y;
161    assign Y = A ^ B;
162endmodule