Flip-flop cells

The cell types $_DFF_N_ and $_DFF_P_ represent d-type flip-flops.

Table 9 Cell types for basic flip-flops

Verilog	Cell Type
always @(negedge C) Q <= D	$_DFF_N_
always @(posedge C) Q <= D	$_DFF_P_

The cell types $_DFFE_[NP][NP]_ implement d-type flip-flops with enable. The values in the table for these cell types relate to the following Verilog code template.

always @(CLK_EDGE C)
   if (EN == EN_LVL)
      Q <= D;

Table 10 Cell types for gate level logic networks (FFs with enable)

\(ClkEdge\)	\(EnLvl\)	Cell Type
negedge	0	$_DFFE_NN_
negedge	1	$_DFFE_NP_
posedge	0	$_DFFE_PN_
posedge	1	$_DFFE_PP_

The cell types $_DFF_[NP][NP][01]_ implement d-type flip-flops with asynchronous reset. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, and negedge otherwise.

always @(CLK_EDGE C, RST_EDGE R)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else
      Q <= D;

The cell types $_SDFF_[NP][NP][01]_ implement d-type flip-flops with synchronous reset. The values in the table for these cell types relate to the following Verilog code template:

always @(CLK_EDGE C)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else
      Q <= D;

Table 11 Cell types for gate level logic networks (FFs with reset)

\(ClkEdge\)	\(RstLvl\)	\(RstVal\)	Cell Type
negedge	0	0	$_DFF_NN0_, $_SDFF_NN0_
negedge	0	1	$_DFF_NN1_, $_SDFF_NN1_
negedge	1	0	$_DFF_NP0_, $_SDFF_NP0_
negedge	1	1	$_DFF_NP1_, $_SDFF_NP1_
posedge	0	0	$_DFF_PN0_, $_SDFF_PN0_
posedge	0	1	$_DFF_PN1_, $_SDFF_PN1_
posedge	1	0	$_DFF_PP0_, $_SDFF_PP0_
posedge	1	1	$_DFF_PP1_, $_SDFF_PP1_

The cell types $_DFFE_[NP][NP][01][NP]_ implement d-type flip-flops with asynchronous reset and enable. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, and negedge otherwise.

always @(CLK_EDGE C, RST_EDGE R)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else if (EN == EN_LVL)
      Q <= D;

The cell types $_SDFFE_[NP][NP][01][NP]_ implement d-type flip-flops with synchronous reset and enable, with reset having priority over enable. The values in the table for these cell types relate to the following Verilog code template:

always @(CLK_EDGE C)
   if (R == RST_LVL)
      Q <= RST_VAL;
   else if (EN == EN_LVL)
      Q <= D;

The cell types $_SDFFCE_[NP][NP][01][NP]_ implement d-type flip-flops with synchronous reset and enable, with enable having priority over reset. The values in the table for these cell types relate to the following Verilog code template:

always @(CLK_EDGE C)
   if (EN == EN_LVL)
      if (R == RST_LVL)
         Q <= RST_VAL;
      else
         Q <= D;

Table 12 Cell types for gate level logic networks (FFs with reset and enable)

\(ClkEdge\)	\(RstLvl\)	\(RstVal\)	\(EnLvl\)	Cell Type
negedge	0	0	0	$_DFFE_NN0N_, $_SDFFE_NN0N_, $_SDFFCE_NN0N_
negedge	0	0	1	$_DFFE_NN0P_, $_SDFFE_NN0P_, $_SDFFCE_NN0P_
negedge	0	1	0	$_DFFE_NN1N_, $_SDFFE_NN1N_, $_SDFFCE_NN1N_
negedge	0	1	1	$_DFFE_NN1P_, $_SDFFE_NN1P_, $_SDFFCE_NN1P_
negedge	1	0	0	$_DFFE_NP0N_, $_SDFFE_NP0N_, $_SDFFCE_NP0N_
negedge	1	0	1	$_DFFE_NP0P_, $_SDFFE_NP0P_, $_SDFFCE_NP0P_
negedge	1	1	0	$_DFFE_NP1N_, $_SDFFE_NP1N_, $_SDFFCE_NP1N_
negedge	1	1	1	$_DFFE_NP1P_, $_SDFFE_NP1P_, $_SDFFCE_NP1P_
posedge	0	0	0	$_DFFE_PN0N_, $_SDFFE_PN0N_, $_SDFFCE_PN0N_
posedge	0	0	1	$_DFFE_PN0P_, $_SDFFE_PN0P_, $_SDFFCE_PN0P_
posedge	0	1	0	$_DFFE_PN1N_, $_SDFFE_PN1N_, $_SDFFCE_PN1N_
posedge	0	1	1	$_DFFE_PN1P_, $_SDFFE_PN1P_, $_SDFFCE_PN1P_
posedge	1	0	0	$_DFFE_PP0N_, $_SDFFE_PP0N_, $_SDFFCE_PP0N_
posedge	1	0	1	$_DFFE_PP0P_, $_SDFFE_PP0P_, $_SDFFCE_PP0P_
posedge	1	1	0	$_DFFE_PP1N_, $_SDFFE_PP1N_, $_SDFFCE_PP1N_
posedge	1	1	1	$_DFFE_PP1P_, $_SDFFE_PP1P_, $_SDFFCE_PP1P_

The cell types $_DFFSR_[NP][NP][NP]_ implement d-type flip-flops with asynchronous set and reset. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, negedge otherwise, and SET_EDGE is posedge if SET_LVL if 1, negedge otherwise.

always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S)
   if (R == RST_LVL)
      Q <= 0;
   else if (S == SET_LVL)
      Q <= 1;
   else
      Q <= D;

Table 13 Cell types for gate level logic networks (FFs with set and reset)

\(ClkEdge\)	\(SetLvl\)	\(RstLvl\)	Cell Type
negedge	0	0	$_DFFSR_NNN_
negedge	0	1	$_DFFSR_NNP_
negedge	1	0	$_DFFSR_NPN_
negedge	1	1	$_DFFSR_NPP_
posedge	0	0	$_DFFSR_PNN_
posedge	0	1	$_DFFSR_PNP_
posedge	1	0	$_DFFSR_PPN_
posedge	1	1	$_DFFSR_PPP_

The cell types $_DFFSRE_[NP][NP][NP][NP]_ implement d-type flip-flops with asynchronous set and reset and enable. The values in the table for these cell types relate to the following Verilog code template, where RST_EDGE is posedge if RST_LVL if 1, negedge otherwise, and SET_EDGE is posedge if SET_LVL if 1, negedge otherwise.

always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S)
   if (R == RST_LVL)
      Q <= 0;
   else if (S == SET_LVL)
      Q <= 1;
   else if (E == EN_LVL)
      Q <= D;

Table 14 Cell types for gate level logic networks (FFs with set and reset and enable)

\(ClkEdge\)	\(SetLvl\)	\(RstLvl\)	\(EnLvl\)	Cell Type
negedge	0	0	0	$_DFFSRE_NNNN_
negedge	0	0	1	$_DFFSRE_NNNP_
negedge	0	1	0	$_DFFSRE_NNPN_
negedge	0	1	1	$_DFFSRE_NNPP_
negedge	1	0	0	$_DFFSRE_NPNN_
negedge	1	0	1	$_DFFSRE_NPNP_
negedge	1	1	0	$_DFFSRE_NPPN_
negedge	1	1	1	$_DFFSRE_NPPP_
posedge	0	0	0	$_DFFSRE_PNNN_
posedge	0	0	1	$_DFFSRE_PNNP_
posedge	0	1	0	$_DFFSRE_PNPN_
posedge	0	1	1	$_DFFSRE_PNPP_
posedge	1	0	0	$_DFFSRE_PPNN_
posedge	1	0	1	$_DFFSRE_PPNP_
posedge	1	1	0	$_DFFSRE_PPPN_
posedge	1	1	1	$_DFFSRE_PPPP_

yosys> help $_ALDFFE_NNN_

A negative edge D-type flip-flop with negative polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d \ - -  0 | d
                - - - -  - | q

Simulation model (verilog)

Listing 234 simcells.v

module \$_ALDFFE_NNN_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(negedge C or negedge L) begin
        if (L == 0)
            Q <= AD;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_ALDFFE_NNP_

A negative edge D-type flip-flop with negative polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d \ - -  1 | d
                - - - -  - | q

Simulation model (verilog)

Listing 235 simcells.v

module \$_ALDFFE_NNP_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(negedge C or negedge L) begin
        if (L == 0)
            Q <= AD;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_ALDFFE_NPN_

A negative edge D-type flip-flop with positive polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d \ - -  0 | d
                - - - -  - | q

Simulation model (verilog)

Listing 236 simcells.v

module \$_ALDFFE_NPN_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(negedge C or posedge L) begin
        if (L == 1)
            Q <= AD;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_ALDFFE_NPP_

A negative edge D-type flip-flop with positive polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d \ - -  1 | d
                - - - -  - | q

Simulation model (verilog)

Listing 237 simcells.v

module \$_ALDFFE_NPP_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(negedge C or posedge L) begin
        if (L == 1)
            Q <= AD;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_ALDFFE_PNN_

A positive edge D-type flip-flop with negative polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d / - -  0 | d
                - - - -  - | q

Simulation model (verilog)

Listing 238 simcells.v

module \$_ALDFFE_PNN_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(posedge C or negedge L) begin
        if (L == 0)
            Q <= AD;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_ALDFFE_PNP_

A positive edge D-type flip-flop with negative polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 0 a  - | a
                d / - -  1 | d
                - - - -  - | q

Simulation model (verilog)

Listing 239 simcells.v

module \$_ALDFFE_PNP_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(posedge C or negedge L) begin
        if (L == 0)
            Q <= AD;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_ALDFFE_PPN_

A positive edge D-type flip-flop with positive polarity async load and negative polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d / - -  0 | d
                - - - -  - | q

Simulation model (verilog)

Listing 240 simcells.v

module \$_ALDFFE_PPN_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(posedge C or posedge L) begin
        if (L == 1)
            Q <= AD;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_ALDFFE_PPP_

A positive edge D-type flip-flop with positive polarity async load and positive polarity clock enable.

Truth table:    D C L AD E | Q
               ------------+---
                - - 1 a  - | a
                d / - -  1 | d
                - - - -  - | q

Simulation model (verilog)

Listing 241 simcells.v

module \$_ALDFFE_PPP_ (D, C, L, AD, E, Q);
    input D, C, L, AD, E;
    output reg Q;
    always @(posedge C or posedge L) begin
        if (L == 1)
            Q <= AD;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_ALDFF_NN_

A negative edge D-type flip-flop with negative polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 0 a  | a
                d \ - -  | d
                - - - -  | q

Simulation model (verilog)

Listing 242 simcells.v

module \$_ALDFF_NN_ (D, C, L, AD, Q);
    input D, C, L, AD;
    output reg Q;
    always @(negedge C or negedge L) begin
        if (L == 0)
            Q <= AD;
        else
            Q <= D;
    end
endmodule

yosys> help $_ALDFF_NP_

A negative edge D-type flip-flop with positive polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 1 a  | a
                d \ - -  | d
                - - - -  | q

Simulation model (verilog)

Listing 243 simcells.v

module \$_ALDFF_NP_ (D, C, L, AD, Q);
    input D, C, L, AD;
    output reg Q;
    always @(negedge C or posedge L) begin
        if (L == 1)
            Q <= AD;
        else
            Q <= D;
    end
endmodule

yosys> help $_ALDFF_PN_

A positive edge D-type flip-flop with negative polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 0 a  | a
                d / - -  | d
                - - - -  | q

Simulation model (verilog)

Listing 244 simcells.v

module \$_ALDFF_PN_ (D, C, L, AD, Q);
    input D, C, L, AD;
    output reg Q;
    always @(posedge C or negedge L) begin
        if (L == 0)
            Q <= AD;
        else
            Q <= D;
    end
endmodule

yosys> help $_ALDFF_PP_

A positive edge D-type flip-flop with positive polarity async load.

Truth table:    D C L AD | Q
               ----------+---
                - - 1 a  | a
                d / - -  | d
                - - - -  | q

Simulation model (verilog)

Listing 245 simcells.v

module \$_ALDFF_PP_ (D, C, L, AD, Q);
    input D, C, L, AD;
    output reg Q;
    always @(posedge C or posedge L) begin
        if (L == 1)
            Q <= AD;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NN0N_

A negative edge D-type flip-flop with negative polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 246 simcells.v

module \$_DFFE_NN0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NN0P_

A negative edge D-type flip-flop with negative polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 247 simcells.v

module \$_DFFE_NN0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NN1N_

A negative edge D-type flip-flop with negative polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 248 simcells.v

module \$_DFFE_NN1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or negedge R) begin
        if (R == 0)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NN1P_

A negative edge D-type flip-flop with negative polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 249 simcells.v

module \$_DFFE_NN1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or negedge R) begin
        if (R == 0)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NN_

A negative edge D-type flip-flop with negative polarity enable.

Truth table:    D C E | Q
               -------+---
                d \ 0 | d
                - - - | q

Simulation model (verilog)

Listing 250 simcells.v

module \$_DFFE_NN_ (D, C, E, Q);
    input D, C, E;
    output reg Q;
    always @(negedge C) begin
        if (!E) Q <= D;
    end
endmodule

yosys> help $_DFFE_NP0N_

A negative edge D-type flip-flop with positive polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 251 simcells.v

module \$_DFFE_NP0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NP0P_

A negative edge D-type flip-flop with positive polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 252 simcells.v

module \$_DFFE_NP0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NP1N_

A negative edge D-type flip-flop with positive polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 253 simcells.v

module \$_DFFE_NP1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or posedge R) begin
        if (R == 1)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NP1P_

A negative edge D-type flip-flop with positive polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 254 simcells.v

module \$_DFFE_NP1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C or posedge R) begin
        if (R == 1)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_NP_

A negative edge D-type flip-flop with positive polarity enable.

Truth table:    D C E | Q
               -------+---
                d \ 1 | d
                - - - | q

Simulation model (verilog)

Listing 255 simcells.v

module \$_DFFE_NP_ (D, C, E, Q);
    input D, C, E;
    output reg Q;
    always @(negedge C) begin
        if (E) Q <= D;
    end
endmodule

yosys> help $_DFFE_PN0N_

A positive edge D-type flip-flop with negative polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 256 simcells.v

module \$_DFFE_PN0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PN0P_

A positive edge D-type flip-flop with negative polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 0
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 257 simcells.v

module \$_DFFE_PN0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PN1N_

A positive edge D-type flip-flop with negative polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 258 simcells.v

module \$_DFFE_PN1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or negedge R) begin
        if (R == 0)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PN1P_

A positive edge D-type flip-flop with negative polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 0 - | 1
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 259 simcells.v

module \$_DFFE_PN1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or negedge R) begin
        if (R == 0)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PN_

A positive edge D-type flip-flop with negative polarity enable.

Truth table:    D C E | Q
               -------+---
                d / 0 | d
                - - - | q

Simulation model (verilog)

Listing 260 simcells.v

module \$_DFFE_PN_ (D, C, E, Q);
    input D, C, E;
    output reg Q;
    always @(posedge C) begin
        if (!E) Q <= D;
    end
endmodule

yosys> help $_DFFE_PP0N_

A positive edge D-type flip-flop with positive polarity reset and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 261 simcells.v

module \$_DFFE_PP0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PP0P_

A positive edge D-type flip-flop with positive polarity reset and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 0
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 262 simcells.v

module \$_DFFE_PP0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PP1N_

A positive edge D-type flip-flop with positive polarity set and negative polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 263 simcells.v

module \$_DFFE_PP1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PP1P_

A positive edge D-type flip-flop with positive polarity set and positive polarity clock enable.

Truth table:    D C R E | Q
               ---------+---
                - - 1 - | 1
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 264 simcells.v

module \$_DFFE_PP1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFE_PP_

A positive edge D-type flip-flop with positive polarity enable.

Truth table:    D C E | Q
               -------+---
                d / 1 | d
                - - - | q

Simulation model (verilog)

Listing 265 simcells.v

module \$_DFFE_PP_ (D, C, E, Q);
    input D, C, E;
    output reg Q;
    always @(posedge C) begin
        if (E) Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NNNN_

A negative edge D-type flip-flop with negative polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 0 - - - | 1
                \ - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 266 simcells.v

module \$_DFFSRE_NNNN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, negedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NNNP_

A negative edge D-type flip-flop with negative polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 0 - - - | 1
                \ - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 267 simcells.v

module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, negedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NNPN_

A negative edge D-type flip-flop with negative polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 0 - - - | 1
                \ - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 268 simcells.v

module \$_DFFSRE_NNPN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, negedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NNPP_

A negative edge D-type flip-flop with negative polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 0 - - - | 1
                \ - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 269 simcells.v

module \$_DFFSRE_NNPP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, negedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NPNN_

A negative edge D-type flip-flop with positive polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 1 - - - | 1
                \ - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 270 simcells.v

module \$_DFFSRE_NPNN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, posedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NPNP_

A negative edge D-type flip-flop with positive polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 1 - - - | 1
                \ - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 271 simcells.v

module \$_DFFSRE_NPNP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, posedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NPPN_

A negative edge D-type flip-flop with positive polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 1 - - - | 1
                \ - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 272 simcells.v

module \$_DFFSRE_NPPN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, posedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_NPPP_

A negative edge D-type flip-flop with positive polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 1 - - - | 1
                \ - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 273 simcells.v

module \$_DFFSRE_NPPP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(negedge C, posedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PNNN_

A positive edge D-type flip-flop with negative polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 0 - - - | 1
                / - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 274 simcells.v

module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, negedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PNNP_

A positive edge D-type flip-flop with negative polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 0 - - - | 1
                / - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 275 simcells.v

module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, negedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PNPN_

A positive edge D-type flip-flop with negative polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 0 - - - | 1
                / - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 276 simcells.v

module \$_DFFSRE_PNPN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, negedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PNPP_

A positive edge D-type flip-flop with negative polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 0 - - - | 1
                / - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 277 simcells.v

module \$_DFFSRE_PNPP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, negedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PPNN_

A positive edge D-type flip-flop with positive polarity set, negative polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 1 - - - | 1
                / - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 278 simcells.v

module \$_DFFSRE_PPNN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, posedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PPNP_

A positive edge D-type flip-flop with positive polarity set, negative polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 0 - - | 0
                - 1 - - - | 1
                / - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 279 simcells.v

module \$_DFFSRE_PPNP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, posedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PPPN_

A positive edge D-type flip-flop with positive polarity set, positive polarity reset and negative polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 1 - - - | 1
                / - - 0 d | d
                - - - - - | q

Simulation model (verilog)

Listing 280 simcells.v

module \$_DFFSRE_PPPN_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, posedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_DFFSRE_PPPP_

A positive edge D-type flip-flop with positive polarity set, positive polarity reset and positive polarity clock enable.

Truth table:    C S R E D | Q
               -----------+---
                - - 1 - - | 0
                - 1 - - - | 1
                / - - 1 d | d
                - - - - - | q

Simulation model (verilog)

Listing 281 simcells.v

module \$_DFFSRE_PPPP_ (C, S, R, E, D, Q);
    input C, S, R, E, D;
    output reg Q;
    always @(posedge C, posedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
            else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_NNN_

A negative edge D-type flip-flop with negative polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 0 - | 0
                - 0 - - | 1
                \ - - d | d
                - - - - | q

Simulation model (verilog)

Listing 282 simcells.v

module \$_DFFSR_NNN_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(negedge C, negedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_NNP_

A negative edge D-type flip-flop with negative polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 1 - | 0
                - 0 - - | 1
                \ - - d | d
                - - - - | q

Simulation model (verilog)

Listing 283 simcells.v

module \$_DFFSR_NNP_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(negedge C, negedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_NPN_

A negative edge D-type flip-flop with positive polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 0 - | 0
                - 1 - - | 1
                \ - - d | d
                - - - - | q

Simulation model (verilog)

Listing 284 simcells.v

module \$_DFFSR_NPN_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(negedge C, posedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_NPP_

A negative edge D-type flip-flop with positive polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 1 - | 0
                - 1 - - | 1
                \ - - d | d
                - - - - | q

Simulation model (verilog)

Listing 285 simcells.v

module \$_DFFSR_NPP_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(negedge C, posedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_PNN_

A positive edge D-type flip-flop with negative polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 0 - | 0
                - 0 - - | 1
                / - - d | d
                - - - - | q

Simulation model (verilog)

Listing 286 simcells.v

module \$_DFFSR_PNN_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(posedge C, negedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_PNP_

A positive edge D-type flip-flop with negative polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 1 - | 0
                - 0 - - | 1
                / - - d | d
                - - - - | q

Simulation model (verilog)

Listing 287 simcells.v

module \$_DFFSR_PNP_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(posedge C, negedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_PPN_

A positive edge D-type flip-flop with positive polarity set and negative polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 0 - | 0
                - 1 - - | 1
                / - - d | d
                - - - - | q

Simulation model (verilog)

Listing 288 simcells.v

module \$_DFFSR_PPN_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(posedge C, posedge S, negedge R) begin
        if (R == 0)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFFSR_PPP_

A positive edge D-type flip-flop with positive polarity set and positive polarity reset.

Truth table:    C S R D | Q
               ---------+---
                - - 1 - | 0
                - 1 - - | 1
                / - - d | d
                - - - - | q

Simulation model (verilog)

Listing 289 simcells.v

module \$_DFFSR_PPP_ (C, S, R, D, Q);
    input C, S, R, D;
    output reg Q;
    always @(posedge C, posedge S, posedge R) begin
        if (R == 1)
            Q <= 0;
        else if (S == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_NN0_

A negative edge D-type flip-flop with negative polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 0 | 0
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 290 simcells.v

module \$_DFF_NN0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C or negedge R) begin
        if (R == 0)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_NN1_

A negative edge D-type flip-flop with negative polarity set.

Truth table:    D C R | Q
               -------+---
                - - 0 | 1
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 291 simcells.v

module \$_DFF_NN1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C or negedge R) begin
        if (R == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_NP0_

A negative edge D-type flip-flop with positive polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 1 | 0
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 292 simcells.v

module \$_DFF_NP0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C or posedge R) begin
        if (R == 1)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_NP1_

A negative edge D-type flip-flop with positive polarity set.

Truth table:    D C R | Q
               -------+---
                - - 1 | 1
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 293 simcells.v

module \$_DFF_NP1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C or posedge R) begin
        if (R == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_N_

A negative edge D-type flip-flop.

Truth table:    D C | Q
               -----+---
                d \ | d
                - - | q

Simulation model (verilog)

Listing 294 simcells.v

module \$_DFF_N_ (D, C, Q);
    input D, C;
    output reg Q;
    always @(negedge C) begin
        Q <= D;
    end
endmodule

yosys> help $_DFF_PN0_

A positive edge D-type flip-flop with negative polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 0 | 0
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 295 simcells.v

module \$_DFF_PN0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C or negedge R) begin
        if (R == 0)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_PN1_

A positive edge D-type flip-flop with negative polarity set.

Truth table:    D C R | Q
               -------+---
                - - 0 | 1
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 296 simcells.v

module \$_DFF_PN1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C or negedge R) begin
        if (R == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_PP0_

A positive edge D-type flip-flop with positive polarity reset.

Truth table:    D C R | Q
               -------+---
                - - 1 | 0
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 297 simcells.v

module \$_DFF_PP0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_PP1_

A positive edge D-type flip-flop with positive polarity set.

Truth table:    D C R | Q
               -------+---
                - - 1 | 1
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 298 simcells.v

module \$_DFF_PP1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C or posedge R) begin
        if (R == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_DFF_P_

A positive edge D-type flip-flop.

Truth table:    D C | Q
               -----+---
                d / | d
                - - | q

Simulation model (verilog)

Listing 299 simcells.v

module \$_DFF_P_ (D, C, Q);
    input D, C;
    output reg Q;
    always @(posedge C) begin
        Q <= D;
    end
endmodule

yosys> help $_FF_

A D-type flip-flop that is clocked from the implicit global clock. (This cell type is usually only used in netlists for formal verification.)

Simulation model (verilog)

Listing 300 simcells.v

module \$_FF_ (D, Q);
    input D;
    output reg Q;
    always @($global_clock) begin
        Q <= D;
    end
endmodule

yosys> help $_SDFFCE_NN0N_

A negative edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 0 | 0
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 301 simcells.v

module \$_SDFFCE_NN0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 0) begin
            if (R == 0)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_NN0P_

A negative edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 1 | 0
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 302 simcells.v

module \$_SDFFCE_NN0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 1) begin
            if (R == 0)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_NN1N_

A negative edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 0 | 1
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 303 simcells.v

module \$_SDFFCE_NN1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 0) begin
            if (R == 0)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_NN1P_

A negative edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 1 | 1
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 304 simcells.v

module \$_SDFFCE_NN1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 1) begin
            if (R == 0)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_NP0N_

A negative edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 0 | 0
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 305 simcells.v

module \$_SDFFCE_NP0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 0) begin
            if (R == 1)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_NP0P_

A negative edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 1 | 0
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 306 simcells.v

module \$_SDFFCE_NP0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 1) begin
            if (R == 1)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_NP1N_

A negative edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 0 | 1
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 307 simcells.v

module \$_SDFFCE_NP1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 0) begin
            if (R == 1)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_NP1P_

A negative edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 1 | 1
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 308 simcells.v

module \$_SDFFCE_NP1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (E == 1) begin
            if (R == 1)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PN0N_

A positive edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 0 | 0
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 309 simcells.v

module \$_SDFFCE_PN0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 0) begin
            if (R == 0)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PN0P_

A positive edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 1 | 0
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 310 simcells.v

module \$_SDFFCE_PN0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 1) begin
            if (R == 0)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PN1N_

A positive edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 0 | 1
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 311 simcells.v

module \$_SDFFCE_PN1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 0) begin
            if (R == 0)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PN1P_

A positive edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 1 | 1
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 312 simcells.v

module \$_SDFFCE_PN1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 1) begin
            if (R == 0)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PP0N_

A positive edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 0 | 0
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 313 simcells.v

module \$_SDFFCE_PP0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 0) begin
            if (R == 1)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PP0P_

A positive edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 1 | 0
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 314 simcells.v

module \$_SDFFCE_PP0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 1) begin
            if (R == 1)
                Q <= 0;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PP1N_

A positive edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 0 | 1
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 315 simcells.v

module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 0) begin
            if (R == 1)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFCE_PP1P_

A positive edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with clock enable having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 1 | 1
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 316 simcells.v

module \$_SDFFCE_PP1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (E == 1) begin
            if (R == 1)
                Q <= 1;
            else
                Q <= D;
        end
    end
endmodule

yosys> help $_SDFFE_NN0N_

A negative edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 0
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 317 simcells.v

module \$_SDFFE_NN0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 0)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_NN0P_

A negative edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 0
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 318 simcells.v

module \$_SDFFE_NN0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 0)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_NN1N_

A negative edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 1
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 319 simcells.v

module \$_SDFFE_NN1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 0)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_NN1P_

A negative edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 0 - | 1
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 320 simcells.v

module \$_SDFFE_NN1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 0)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_NP0N_

A negative edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 0
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 321 simcells.v

module \$_SDFFE_NP0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 1)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_NP0P_

A negative edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 0
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 322 simcells.v

module \$_SDFFE_NP0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 1)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_NP1N_

A negative edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 1
                d \ - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 323 simcells.v

module \$_SDFFE_NP1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 1)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_NP1P_

A negative edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - \ 1 - | 1
                d \ - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 324 simcells.v

module \$_SDFFE_NP1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(negedge C) begin
        if (R == 1)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PN0N_

A positive edge D-type flip-flop with negative polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 0
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 325 simcells.v

module \$_SDFFE_PN0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 0)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PN0P_

A positive edge D-type flip-flop with negative polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 0
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 326 simcells.v

module \$_SDFFE_PN0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 0)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PN1N_

A positive edge D-type flip-flop with negative polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 1
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 327 simcells.v

module \$_SDFFE_PN1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 0)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PN1P_

A positive edge D-type flip-flop with negative polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 0 - | 1
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 328 simcells.v

module \$_SDFFE_PN1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 0)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PP0N_

A positive edge D-type flip-flop with positive polarity synchronous reset and negative polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 0
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 329 simcells.v

module \$_SDFFE_PP0N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 1)
            Q <= 0;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PP0P_

A positive edge D-type flip-flop with positive polarity synchronous reset and positive polarity clock enable (with reset having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 0
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 330 simcells.v

module \$_SDFFE_PP0P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 1)
            Q <= 0;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PP1N_

A positive edge D-type flip-flop with positive polarity synchronous set and negative polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 1
                d / - 0 | d
                - - - - | q

Simulation model (verilog)

Listing 331 simcells.v

module \$_SDFFE_PP1N_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 1)
            Q <= 1;
        else if (E == 0)
            Q <= D;
    end
endmodule

yosys> help $_SDFFE_PP1P_

A positive edge D-type flip-flop with positive polarity synchronous set and positive polarity clock enable (with set having priority).

Truth table:    D C R E | Q
               ---------+---
                - / 1 - | 1
                d / - 1 | d
                - - - - | q

Simulation model (verilog)

Listing 332 simcells.v

module \$_SDFFE_PP1P_ (D, C, R, E, Q);
    input D, C, R, E;
    output reg Q;
    always @(posedge C) begin
        if (R == 1)
            Q <= 1;
        else if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_SDFF_NN0_

A negative edge D-type flip-flop with negative polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - \ 0 | 0
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 333 simcells.v

module \$_SDFF_NN0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C) begin
        if (R == 0)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_SDFF_NN1_

A negative edge D-type flip-flop with negative polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - \ 0 | 1
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 334 simcells.v

module \$_SDFF_NN1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C) begin
        if (R == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_SDFF_NP0_

A negative edge D-type flip-flop with positive polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - \ 1 | 0
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 335 simcells.v

module \$_SDFF_NP0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C) begin
        if (R == 1)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_SDFF_NP1_

A negative edge D-type flip-flop with positive polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - \ 1 | 1
                d \ - | d
                - - - | q

Simulation model (verilog)

Listing 336 simcells.v

module \$_SDFF_NP1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(negedge C) begin
        if (R == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_SDFF_PN0_

A positive edge D-type flip-flop with negative polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - / 0 | 0
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 337 simcells.v

module \$_SDFF_PN0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C) begin
        if (R == 0)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_SDFF_PN1_

A positive edge D-type flip-flop with negative polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - / 0 | 1
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 338 simcells.v

module \$_SDFF_PN1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C) begin
        if (R == 0)
            Q <= 1;
        else
            Q <= D;
    end
endmodule

yosys> help $_SDFF_PP0_

A positive edge D-type flip-flop with positive polarity synchronous reset.

Truth table:    D C R | Q
               -------+---
                - / 1 | 0
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 339 simcells.v

module \$_SDFF_PP0_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C) begin
        if (R == 1)
            Q <= 0;
        else
            Q <= D;
    end
endmodule

yosys> help $_SDFF_PP1_

A positive edge D-type flip-flop with positive polarity synchronous set.

Truth table:    D C R | Q
               -------+---
                - / 1 | 1
                d / - | d
                - - - | q

Simulation model (verilog)

Listing 340 simcells.v

module \$_SDFF_PP1_ (D, C, R, Q);
    input D, C, R;
    output reg Q;
    always @(posedge C) begin
        if (R == 1)
            Q <= 1;
        else
            Q <= D;
    end
endmodule