Unary operators

All unary RTL cells have one input port A and one output port Y. They also have the following parameters:

A_SIGNED

Set to a non-zero value if the input A is signed and therefore should be sign-extended when needed.

A_WIDTH

The width of the input port A.

Y_WIDTH

The width of the output port Y.

Table 4 Cell types for unary operators with their corresponding Verilog expressions.

Verilog	Cell Type
Y = ~A	$not
Y = +A	$pos
Y = -A	$neg
Y = &A	$reduce_and
Y = |A	$reduce_or
Y = ^A	$reduce_xor
Y = ~^A	$reduce_xnor
Y = |A	$reduce_bool
Y = !A	$logic_not

For the unary cells that output a logical value ($reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool, $logic_not), when the Y_WIDTH parameter is greater than 1, the output is zero-extended, and only the least significant bit varies.

Note that $reduce_or and $reduce_bool generally represent the same logic function. But the read_verilog frontend will generate them in different situations. A $reduce_or cell is generated when the prefix | operator is being used. A $reduce_bool cell is generated when a bit vector is used as a condition in an if-statement or ?:-expression.

yosys> help $buf

A simple coarse-grain buffer cell type for the experimental buffered-normalized mode. Note this cell does’t get removed by ‘opt_clean’ and is not recommended for general use.

Properties:

is_evaluable

Simulation model (verilog)

Listing 114 simlib.v

module \$buf (A, Y);

    parameter WIDTH = 0;

    input [WIDTH-1:0] A;
    output [WIDTH-1:0] Y;

    assign Y = A;

endmodule

yosys> help $logic_not

A logical inverter. This corresponds to the Verilog unary prefix ‘!’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 115 simlib.v

module \$logic_not (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = !$signed(A);
        end else begin:BLOCK2
            assign Y = !A;
        end
    endgenerate

endmodule

yosys> help $neg

An arithmetic inverter. This corresponds to the Verilog unary prefix ‘-’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 116 simlib.v

module \$neg (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = -$signed(A);
        end else begin:BLOCK2
            assign Y = -A;
        end
    endgenerate

endmodule

yosys> help $not

Bit-wise inverter

This corresponds to the Verilog unary prefix ‘~’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 117 simlib.v

module \$not (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = ~$signed(A);
        end else begin:BLOCK2
            assign Y = ~A;
        end
    endgenerate

endmodule

yosys> help $pos

A buffer. This corresponds to the Verilog unary prefix ‘+’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 118 simlib.v

module \$pos (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = $signed(A);
        end else begin:BLOCK2
            assign Y = A;
        end
    endgenerate

endmodule

yosys> help $reduce_and

An AND reduction. This corresponds to the Verilog unary prefix ‘&’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 119 simlib.v

module \$reduce_and (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = &$signed(A);
        end else begin:BLOCK2
            assign Y = &A;
        end
    endgenerate

endmodule

yosys> help $reduce_bool

An OR reduction. This cell type is used instead of $reduce_or when a signal is implicitly converted to a boolean signal, e.g. for operands of ‘&&’ and ‘||’.

Properties:

is_evaluable

Simulation model (verilog)

Listing 120 simlib.v

module \$reduce_bool (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = !(!$signed(A));
        end else begin:BLOCK2
            assign Y = !(!A);
        end
    endgenerate

endmodule

yosys> help $reduce_or

An OR reduction. This corresponds to the Verilog unary prefix ‘|’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 121 simlib.v

module \$reduce_or (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = |$signed(A);
        end else begin:BLOCK2
            assign Y = |A;
        end
    endgenerate

endmodule

yosys> help $reduce_xnor

A XNOR reduction. This corresponds to the Verilog unary prefix ‘~^’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 122 simlib.v

module \$reduce_xnor (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = ~^$signed(A);
        end else begin:BLOCK2
            assign Y = ~^A;
        end
    endgenerate

endmodule

yosys> help $reduce_xor

A XOR reduction. This corresponds to the Verilog unary prefix ‘^’ operator.

Properties:

is_evaluable

Simulation model (verilog)

Listing 123 simlib.v

module \$reduce_xor (A, Y);

    parameter A_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    output [Y_WIDTH-1:0] Y;

    generate
        if (A_SIGNED) begin:BLOCK1
            assign Y = ^$signed(A);
        end else begin:BLOCK2
            assign Y = ^A;
        end
    endgenerate

endmodule